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ZHCS409G June 2010 – September 2020 MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

ZQW|113
- MPBG674
ZCA|113
- MPBGAJ3A
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

8.33 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
(see Figure 8-13 and Figure 8-14)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE low to clock	PMMCOREV = 0	1.8 V	11		ns
		PMMCOREV = 0	3 V	8
		PMMCOREV = 3	2.4 V	7
		PMMCOREV = 3	3 V	6
t_STE,LAG	STE lag time, Last clock to STE high	PMMCOREV = 0	1.8 V	3		ns
		PMMCOREV = 0	3 V	3
		PMMCOREV = 3	2.4 V	3
		PMMCOREV = 3	3 V	3
t_STE,ACC	STE access time, STE low to SOMI data out	PMMCOREV = 0	1.8 V		66	ns
		PMMCOREV = 0	3 V		50
		PMMCOREV = 3	2.4 V		36
		PMMCOREV = 3	3 V		30
t_STE,DIS	STE disable time, STE high to SOMI high impedance	PMMCOREV = 0	1.8 V		30	ns
		PMMCOREV = 0	3 V		23
		PMMCOREV = 3	2.4 V		16
		PMMCOREV = 3	3 V		13
t_SU,SI	SIMO input data setup time	PMMCOREV = 0	1.8 V	5		ns
		PMMCOREV = 0	3 V	5
		PMMCOREV = 3	2.4 V	2
		PMMCOREV = 3	3 V	2
t_HD,SI	SIMO input data hold time	PMMCOREV = 0	1.8 V	5		ns
		PMMCOREV = 0	3 V	5
		PMMCOREV = 3	2.4 V	5
		PMMCOREV = 3	3 V	5
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF, PMMCOREV = 0	1.8 V		76	ns
		UCLK edge to SOMI valid, C_L = 20 pF, PMMCOREV = 0	3 V		60
		UCLK edge to SOMI valid, C_L = 20 pF, PMMCOREV = 3	2.4 V		44
		UCLK edge to SOMI valid, C_L = 20 pF, PMMCOREV = 3	3 V		40
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF, PMMCOREV = 0	1.8 V	18		ns
		C_L = 20 pF, PMMCOREV = 0	3 V	12
		C_L = 20 pF, PMMCOREV = 3	2.4 V	10
		C_L = 20 pF, PMMCOREV = 3	3 V	8

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(USCI), t_{SU,MI(Master)} + t_{VALID,SO(USCI)})
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-13 and Figure 8-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8-13 and Figure 8-14.

Figure 8-13 SPI Slave Mode, CKPH = 0

Figure 8-14 SPI Slave Mode, CKPH = 1