米6体育平台手机版

ZHCSDG4A February 2015 – October 2018 MSP430F6720A , MSP430F6721A , MSP430F6723A , MSP430F6724A , MSP430F6725A , MSP430F6726A , MSP430F6730A , MSP430F6731A , MSP430F6733A , MSP430F6734A , MSP430F6735A , MSP430F6736A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PN|80
- MTQF010B
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

订购信息

Table 5-31 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock		2.0 V	4		ns
t_STE,LEAD	STE lead time, STE active to clock		3.0 V	3		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		2.0 V	0		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		3.0 V	0		ns
t_STE,ACC	STE access time, STE active to SOMI data out		2.0 V		46	ns
t_STE,ACC	STE access time, STE active to SOMI data out		3.0 V		24	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		2.0 V		38	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		3.0 V		25	ns
t_SU,SI	SIMO input data setup time		2.0 V	2		ns
t_SU,SI	SIMO input data setup time		3.0 V	1		ns
t_HD,SI	SIMO input data hold time		2.0 V	2		ns
t_HD,SI	SIMO input data hold time		3.0 V	2		ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2.0 V		55	ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3.0 V		32	ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	2.0 V	24		ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	3.0 V	16		ns

(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI = max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)})
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 5-13 and Figure 5-14.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 5-15 and Figure 5-16.

MSP430F6736A MSP430F6735A MSP430F6734A MSP430F6733A MSP430F6731A MSP430F6730A MSP430F6726A MSP430F6725A MSP430F6724A MSP430F6723A MSP430F6721A MSP430F6720A slase46-eUSCI_slave_CKPH0.gif

Figure 5-15 SPI Slave Mode, CKPH = 0

Figure 5-16 SPI Slave Mode, CKPH = 1

Table 5-32 lists the characteristics of the eUSCI in I²C mode.