米6体育平台手机版

ZHCS707D December 2011 – September 2018 MSP430F6720 , MSP430F6721 , MSP430F6723 , MSP430F6724 , MSP430F6725 , MSP430F6726 , MSP430F6730 , MSP430F6731 , MSP430F6733 , MSP430F6734 , MSP430F6735 , MSP430F6736

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PN|80
- MTQF010B
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

订购信息

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Family Members⁽²⁾⁽³⁾

DEVICE	FLASH (KB)	SRAM (KB)	SD24_B CONVERTERS	ADC10_A CHANNELS	Timer_A⁽¹⁾	eUSCI_A: UART, IrDA, SPI	eUSCI_B: SPI, I²C	I/Os	PACKAGE
MSP430F6736IPZ	128	8	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6735IPZ	128	4	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6734IPZ	96	4	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6733IPZ	64	4	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6731IPZ	32	2	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6730IPZ	16	1	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6726IPZ	128	8	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6725IPZ	128	4	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6724IPZ	96	4	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6723IPZ	64	4	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6721IPZ	32	2	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6720IPZ	16	1	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6736IPN	128	8	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6735IPN	128	4	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6734IPN	96	4	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6733IPN	64	4	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6731IPN	32	2	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6730IPN	16	1	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6726IPN	128	8	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6725IPN	128	4	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6724IPN	96	4	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6723IPN	64	4	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6721IPN	32	2	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6720IPN	16	1	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(2) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.

(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.