米6体育平台手机版

ZHCSDG4A February 2015 – October 2018 MSP430F6720A , MSP430F6721A , MSP430F6723A , MSP430F6724A , MSP430F6725A , MSP430F6726A , MSP430F6730A , MSP430F6731A , MSP430F6733A , MSP430F6734A , MSP430F6735A , MSP430F6736A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PN|80
- MTQF010B
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

订购信息

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison⁽²⁾⁽³⁾

DEVICE	FLASH (KB)	SRAM (KB)	SD24_B CONVERTERS	ADC10_A CHANNELS	Timer_A⁽¹⁾	eUSCI_A: UART, IrDA, SPI	eUSCI_B: SPI, I²C	I/Os	PACKAGE
MSP430F6736AIPZ	128	8	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6735AIPZ	128	4	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6734AIPZ	96	4	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6733AIPZ	64	4	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6731AIPZ	32	2	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6730AIPZ	16	1	3	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6726AIPZ	128	8	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6725AIPZ	128	4	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6724AIPZ	96	4	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6723AIPZ	64	4	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6721AIPZ	32	2	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6720AIPZ	16	1	2	6 ext, 2 int	3, 2, 2, 2	3	1	72	100 PZ
MSP430F6736AIPN	128	8	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6735AIPN	128	4	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6734AIPN	96	4	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6733AIPN	64	4	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6731AIPN	32	2	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6730AIPN	16	1	3	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6726AIPN	128	8	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6725AIPN	128	4	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6724AIPN	96	4	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6723AIPN	64	4	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6721AIPN	32	2	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN
MSP430F6720AIPN	16	1	2	3 ext, 2 int	3, 2, 2, 2	3	1	52	80 PN

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(2) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.

(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.