米6体育平台手机版

ZHCSDG4A February 2015 – October 2018 MSP430F6720A , MSP430F6721A , MSP430F6723A , MSP430F6724A , MSP430F6725A , MSP430F6726A , MSP430F6730A , MSP430F6731A , MSP430F6733A , MSP430F6734A , MSP430F6735A , MSP430F6736A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PN|80
- MTQF010B
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power-Up External Reset Watchdog Time-out, Key Violation Flash Memory Key Violation	WDTIFG, KEYV (SYSRSTIV)⁽¹⁾⁽²⁾	Reset	0FFFEh	63, highest
System NMI PMM Vacant Memory Access JTAG Mailbox	SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) ⁽¹⁾⁽³⁾	(Non)maskable	0FFFCh	62
User NMI NMI Oscillator Fault Flash Memory Access Violation Supply Switch	NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG (SYSUNIV)⁽¹⁾⁽³⁾	(Non)maskable	0FFFAh	61
Watchdog Timer_A Interval Timer Mode	WDTIFG	Maskable	0FFF8h	60
eUSCI_A0 Receive or Transmit	UCA0RXIFG, UCA0TXIFG (UCA0IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF6h	59
eUSCI_B0 Receive or Transmit	UCB0RXIFG, UCB0TXIFG (UCB0IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF4h	58
ADC10_A	ADC10IFG0, ADC10INIFG, ADC10LOIFG, ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG (ADC10IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF2h	57
SD24_B	SD24_B Interrupt Flags (SD24IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF0h	56
Timer TA0	TA0CCR0 CCIFG0⁽⁴⁾	Maskable	0FFEEh	55
Timer TA0	TA0CCR1 CCIFG1, TA0CCR2 CCIFG2, TA0IFG (TA0IV)⁽¹⁾⁽⁴⁾	Maskable	0FFECh	54
eUSCI_A1 Receive or Transmit	UCA1RXIFG, UCA1TXIFG (UCA1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFEAh	53
eUSCI_A2 Receive or Transmit	UCA2RXIFG, UCA2TXIFG (UCA2IV)⁽¹⁾⁽⁴⁾	Maskable	0FFE8h	52
Auxiliary Supplies	Auxiliary Supplies Interrupt Flags (AUXIV)⁽¹⁾⁽⁴⁾	Maskable	0FFE6h	51
DMA	DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)⁽¹⁾⁽⁴⁾	Maskable	0FFE4h	50
Timer TA1	TA1CCR0 CCIFG0⁽⁴⁾	Maskable	0FFE2h	49
Timer TA1	TA1CCR1 CCIFG1, TA1IFG (TA1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFE0h	48
I/O Port P1	P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFDEh	47
Timer TA2	TA2CCR0 CCIFG0⁽⁴⁾	Maskable	0FFDCh	46
Timer TA2	TA2CCR1 CCIFG1, TA2IFG (TA2IV)⁽¹⁾⁽⁴⁾	Maskable	0FFDAh	45
I/O Port P2	P2IFG.0 to P2IFG.7 (P2IV)⁽¹⁾⁽⁴⁾	Maskable	0FFD8h	44
Timer TA3	TA3CCR0 CCIFG0⁽⁴⁾	Maskable	0FFD6h	43
Timer TA3	TA3CCR1 CCIFG1, TA3IFG (TA3IV)⁽¹⁾⁽⁴⁾	Maskable	0FFD4h	42
LCD_C	LCD_C Interrupt Flags (LCDCIV)⁽¹⁾⁽⁴⁾	Maskable	0FFD2h	41
RTC_C	RTCOFIFG, RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)⁽¹⁾⁽⁴⁾	Maskable	0FFD0h	40
Reserved	Reserved⁽⁵⁾		0FFCEh	39
			⋮	⋮
			0FF80h	0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4) Interrupt flags are located in the module.

(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.