ZHCSDE8A February   2015  – October 2018 MSP430F67621A , MSP430F67641A

PRODUCTION DATA.  

1. 1器件概述
   1. 1.1 特性
   2. 1.2 应用范围
   3. 1.3 说明
   4. 1.4 应用图表
2. 2修订历史记录
3. 3Device Comparison
   1. 3.1 Related Products
4. 4Terminal Configuration and Functions
   1. 4.1 Pin Diagrams
   2. 4.2 Pin Attributes
   3. 4.3 Signal Descriptions
      1. Table 4-3 Signal Descriptions – PZ Package
      2. Table 4-4 Signal Descriptions – PN Package
   4. 4.4 Pin Multiplexing
   5. 4.5 Buffer Type
   6. 4.6 Connection of Unused Pins
5. 5Specifications
   1. 5.1 Absolute Maximum Ratings
   2. 5.2 ESD Ratings
   3. 5.3 Recommended Operating Conditions
   4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
   5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
   6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
   7. 5.7 Thermal Resistance Characteristics
   8. 5.8 Timing and Switching Characteristics
      1. 5.8.1  Power Supply Sequencing
      2. 5.8.2  Reset Timing
         1. Table 5-1 Wake-up Times From Low-Power Modes and Reset
      3. 5.8.3  Clock Specifications
         1. Table 5-2 Crystal Oscillator, XT1, Low-Frequency Mode
         2. Table 5-3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
         3. Table 5-4 Internal Reference, Low-Frequency Oscillator (REFO)
         4. Table 5-5 DCO Frequency
      4. 5.8.4  Digital I/O Ports
         1. Table 5-6  Schmitt-Trigger Inputs, General-Purpose I/O
         2. Table 5-7  Inputs, Ports P1 and P2
         3. Table 5-8  Leakage Current, General-Purpose I/O
         4. Table 5-9  Outputs, General-Purpose I/O (Full Drive Strength)
         5. 5.8.4.1    Typical Characteristics, General-Purpose I/O (Full Drive Strength)
         6. Table 5-10 Outputs, General-Purpose I/O (Reduced Drive Strength)
         7. 5.8.4.2    Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)
         8. Table 5-11 Output Frequency, General-Purpose I/O
      5. 5.8.5  Power-Management Module (PMM)
         1. Table 5-12 PMM, Brownout Reset (BOR)
         2. Table 5-13 PMM, Core Voltage
         3. Table 5-14 PMM, SVS High Side
         4. Table 5-15 PMM, SVM High Side
         5. Table 5-16 PMM, SVS Low Side
         6. Table 5-17 PMM, SVM Low Side
      6. 5.8.6  Auxiliary Supplies Module
         1. Table 5-18 Auxiliary Supplies, Recommended Operating Conditions
         2. Table 5-19 Auxiliary Supplies, AUX3 (Backup Subsystem) Currents
         3. Table 5-20 Auxiliary Supplies, Auxiliary Supply Monitor
         4. Table 5-21 Auxiliary Supplies, Switch ON-Resistance
         5. Table 5-22 Auxiliary Supplies, Switching Time
         6. Table 5-23 Auxiliary Supplies, Switch Leakage
         7. Table 5-24 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
         8. Table 5-25 Auxiliary Supplies, Charge-Limiting Resistor
      7. 5.8.7  Timer_A Module
         1. Table 5-26 Timer_A
      8. 5.8.8  eUSCI Module
         1. Table 5-27 eUSCI (UART Mode) Clock Frequency
         2. Table 5-28 eUSCI (UART Mode) Switching Characteristics
         3. Table 5-29 eUSCI (SPI Master Mode) Clock Frequency
         4. Table 5-30 eUSCI (SPI Master Mode) Switching Characteristics
         5. Table 5-31 eUSCI (SPI Slave Mode)
         6. Table 5-32 eUSCI (I2C Mode)
      9. 5.8.9  LCD Controller
         1. Table 5-33 LCD_C Operating Conditions
         2. Table 5-34 LCD_C Electrical Characteristics
      10. 5.8.10 SD24_B Module
          1. Table 5-35 SD24_B Power Supply and Recommended Operating Conditions
          2. Table 5-36 SD24_B Analog Input
          3. Table 5-37 SD24_B Supply Currents
          4. Table 5-38 SD24_B Performance
          5. Table 5-39 SD24_B AC Performance
          6. Table 5-40 SD24_B AC Performance
          7. Table 5-41 SD24_B AC Performance
          8. Table 5-42 SD24_B External Reference Input
      11. 5.8.11 ADC10_A Module
          1. Table 5-43 10-Bit ADC, Power Supply and Input Range Conditions
          2. Table 5-44 10-Bit ADC, Timing Parameters
          3. Table 5-45 10-Bit ADC, Linearity Parameters
          4. Table 5-46 10-Bit ADC, External Reference
      12. 5.8.12 REF Module
          1. Table 5-47 REF, Built-In Reference
      13. 5.8.13 Flash
          1. Table 5-48 Flash Memory
      14. 5.8.14 Emulation and Debug
          1. Table 5-49 JTAG and Spy-Bi-Wire Interface
6. 6Detailed Description
   1. 6.1  Overview
   2. 6.2  Functional Block Diagrams
   3. 6.3  CPU
   4. 6.4  Instruction Set
   5. 6.5  Operating Modes
   6. 6.6  Interrupt Vector Addresses
   7. 6.7  Bootloader (BSL)
   8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
   9. 6.9  Flash Memory
   10. 6.10 RAM
   11. 6.11 Backup RAM
   12. 6.12 Peripherals
       1. 6.12.1  Oscillator and System Clock
       2. 6.12.2  Power-Management Module (PMM)
       3. 6.12.3  Auxiliary Supply System
       4. 6.12.4  Backup Subsystem
       5. 6.12.5  Digital I/O
       6. 6.12.6  Port Mapping Controller
       7. 6.12.7  System Module (SYS)
       8. 6.12.8  Watchdog Timer (WDT_A)
       9. 6.12.9  DMA Controller
       10. 6.12.10 CRC16
       11. 6.12.11 Hardware Multiplier
       12. 6.12.12 Enhanced Universal Serial Communication Interface (eUSCI)
       13. 6.12.13 ADC10_A
       14. 6.12.14 SD24_B
       15. 6.12.15 TA0
       16. 6.12.16 TA1
       17. 6.12.17 TA2
       18. 6.12.18 TA3
       19. 6.12.19 SD24_B Triggers
       20. 6.12.20 ADC10_A Triggers
       21. 6.12.21 Real-Time Clock (RTC_C)
       22. 6.12.22 Reference (REF) Module Voltage Reference
       23. 6.12.23 LCD_C
       24. 6.12.24 Embedded Emulation Module (EEM) (S Version)
   13. 6.13 Input/Output Diagrams
       1. 6.13.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
       2. 6.13.2  Port P1 (P1.2) Input/Output With Schmitt Trigger
       3. 6.13.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
       4. 6.13.4  Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Input/Output With Schmitt Trigger
       5. 6.13.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
       6. 6.13.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (PZ Package Only)
       7. 6.13.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
       8. 6.13.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (PZ Package Only)
       9. 6.13.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (PZ Package Only)
       10. 6.13.10 Port P9 (P9.0), Input/Output With Schmitt Trigger (PZ Package Only)
       11. 6.13.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (PZ Package Only)
       12. 6.13.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (PN Package Only)
       13. 6.13.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PN Package Only)
       14. 6.13.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PN Package Only)
       15. 6.13.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PN Package Only)
       16. 6.13.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
       17. 6.13.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
   14. 6.14 Device Descriptors (TLV)
   15. 6.15 Memory
       1. 6.15.1 Peripheral File Map
   16. 6.16 Identification
       1. 6.16.1 Revision Identification
       2. 6.16.2 Device Identification
       3. 6.16.3 JTAG Identification
7. 7Applications, Implementation, and Layout
8. 8器件和文档支持
   1. 8.1  入门和后续步骤
   2. 8.2  Device Nomenclature
   3. 8.3  工具与软件
   4. 8.4  文档支持
   5. 8.5  相关链接
   6. 8.6  社区资源
   7. 8.7  商标
   8. 8.8  静电放电警告
   9. 8.9  Export Control Notice
   10. 8.10 Glossary
9. 9机械、封装和可订购信息