米6体育平台手机版

ZHCSAU5E September 2012 – September 2018 MSP430F6745 , MSP430F6746 , MSP430F6747 , MSP430F6748 , MSP430F6749 , MSP430F6765 , MSP430F6766 , MSP430F6767 , MSP430F6768 , MSP430F6769 , MSP430F6775 , MSP430F6776 , MSP430F6777 , MSP430F6778 , MSP430F6779

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PEU|128
- MPQF058B
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

5.13 Output Frequency – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MAX	UNIT
f_Px.y	Port output frequency (with load)	See ⁽¹⁾⁽²⁾	V_CC = 1.8 V, PMMCOREVx = 0	16	MHz
f_Px.y	Port output frequency (with load)	See ⁽¹⁾⁽²⁾	V_CC = 3 V, PMMCOREVx = 3	25	MHz
f_{Port_CLK}	Clock output frequency	ACLK, SMCLK, or MCLK, C_L = 20 pF⁽²⁾	V_CC = 1.8 V, PMMCOREVx = 0	16	MHz
f_{Port_CLK}	Clock output frequency	ACLK, SMCLK, or MCLK, C_L = 20 pF⁽²⁾	V_CC = 3 V, PMMCOREVx = 3	25	MHz

(1) A resistive divider with 2 × R1 between V_CC and V_SS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. C_L = 20 pF is connected to the output to V_SS.

(2) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.