米6体育平台手机版

PRODUCTION DATA.

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-15)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_eUSCI	eUSCI input clock frequency	Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10%				f_SYSTEM	MHz
f_SCL	SCL clock frequency		2 V, 3 V	0		400	kHz
t_HD,STA	Hold time (repeated) START	f_SCL = 100 kHz	2 V, 3 V	5.1			µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	2 V, 3 V	1.5			µs
t_SU,STA	Setup time for a repeated START	f_SCL = 100 kHz	2 V, 3 V	5.1			µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	2 V, 3 V	1.4			µs
t_HD,DAT	Data hold time		2 V, 3 V	0.4			µs
t_SU,DAT	Data setup time	f_SCL = 100 kHz	2 V, 3 V	5.0			µs
t_SU,DAT	Data setup time	f_SCL > 100 kHz	2 V, 3 V	1.3			µs
t_SU,STO	Setup time for STOP	f_SCL = 100 kHz	2 V, 3 V	5.2			µs
t_SU,STO	Setup time for STOP	f_SCL > 100 kHz	2 V, 3 V	1.7			µs
t_SP	Pulse duration of spikes suppressed by input filter	UCGLITx = 0	2 V, 3 V	75		220	ns
		UCGLITx = 1		35		120
		UCGLITx = 2		30		60
		UCGLITx = 3		20		35
t_TIMEOUT	Clock low time-out	UCCLTOx = 1	2 V, 3 V		30		ms
		UCCLTOx = 2			33
		UCCLTOx = 3			37

Figure 5-15 I²C Mode Timing