Table 6-1 summarizes the available family members.
Table 6-1 Device Comparison
| DEVICE(1)(2) |
FLASH
(KB) |
SRAM
(KB)(3) |
Timer_A(4) |
Timer_B(5) |
USCI_A:
UART, IrDA, SPI |
USCI_B:
SPI, I2C |
CTSD16
(Ch)(6) |
DAC12_A
(Ch) |
OA |
Comp_B
(channels) |
USB |
I/Os |
PACKAGE |
| MSP430FG6626 |
128 |
8 + 2 |
5, 3, 3 |
7 |
2 |
2 |
10 ext,
5 int |
2 |
2 |
12 |
1 |
73 |
100 PZ, 113 ZCA 113 ZQW |
| MSP430FG6625 |
64 |
8 + 2 |
5, 3, 3 |
7 |
2 |
2 |
10 ext,
5 int |
2 |
2 |
12 |
1 |
73 |
100 PZ, 113 ZCA 113 ZQW |
| MSP430FG6426 |
128 |
10 |
5, 3, 3 |
7 |
2 |
2 |
10 ext,
5 int |
2 |
2 |
12 |
0 |
73 |
100 PZ, 113 ZCA 113 ZQW |
| MSP430FG6425 |
64 |
10 |
5, 3, 3 |
7 |
2 |
2 |
10 ext,
5 int |
2 |
2 |
12 |
0 |
73 |
100 PZ, 113 ZCA 113 ZQW |
(1) For the most current package and ordering information, see the
Package Option Addendum in
Section 12, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
(4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(6) ADC inputs consist of a mix of single ended and differential. See the pinning for available input pairs and types.