ZHCSDO6B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626
PRODUCTION DATA
Figure 9-4 shows the port diagram. Table 9-17 summarizes the selection of the port function.
PIN NAME (P2.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | ||||
---|---|---|---|---|---|---|---|
P2DIR.x | P2SEL.x | P2MAPx | DAC12OPS | DAC12AMPx | |||
P2.0/P2MAP0/DAC0 | 0 | P2.0 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
DAC0 | X | X | = 31 | 1 | >1 | ||
P2.1/P2MAP1/DAC1 | 1 | P2.1 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
DAC1 | X | X | = 31 | 1 | >1 | ||
P2.2/P2MAP2 | 2 | P2.2 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
P2.3/P2MAP3 | 3 | P2.3 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
P2.4/P2MAP4/R03 | 4 | P2.4 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
R03 | X | 1 | = 31 | X | 0 | ||
P2.5/P2MAP5 | 5 | P2.5 (I/O | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
P2.6/P2MAP6/LCDREF/R13 | 6 | P2.6 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
LCDREF/R13 | X | 1 | = 31 | X | 0 | ||
P2.7/P2MAP7/R23 | 7 | P2.7 (I/O) | I: 0; O: 1 | 0 | X | 0 | |
Mapped secondary digital function | X | 1 | ≤ 19 | X | 0 | ||
R23 | X | 1 | = 31 | X | 0 |