米6体育平台手机版

ZHCSDO6B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA

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机械数据 (封装 | 引脚)

PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

8.8.13.4 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_eREF+	Reference input voltage range	DAC12IR = 0⁽¹⁾ ⁽²⁾	2.2 V to 3.6 V		AV_CC / 3	AV_CC + 0.2	V
V_eREF+	Reference input voltage range	DAC12IR = 1⁽³⁾ ⁽⁴⁾	2.2 V to 3.6 V		AV_CC	AV_CC + 0.2	V
Ri_(VREFBG), Ri_(VeREF+)	Reference input resistance	DAC12_0 DAC12IR = DAC12_1 DAC12IR = 0	2.2 V, 3 V	20			MΩ
		DAC12_0 DAC12IR = 1, DAC12_1 DAC12IR = 0			52		kΩ
		DAC12_0 DAC12IR = 0, DAC12_1 DAC12IR = 1			52
		DAC12_0 DAC12IR = DAC12_1 DAC12IR = 1, DAC12_0 DAC12SREFx = DAC12_1 DAC12SREFx⁽⁵⁾			26

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV_CC – V_E(O)] / [3 × (1 + E_G)].

(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).

(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AV_CC – V_E(O)] / (1 + E_G).

(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel and reduce the reference input resistance.

Section 8.8.13.5 and Section 8.8.13.6 list the dynamic specifications of the DAC.