As with any high-resolution ADC, appropriate printed circuit board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the ADC. Therefore, solid decoupling on both the digital and analog supplies is required (best with two capacitors, one 1 µF and one 100 nF [see Section 10.1.1]).

In addition to grounding, ripple and noise spikes on the power-supply lines due to digital switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free design using separate analog and digital ground planes with a single-point connection to achieve high accuracy.

If the internal reference is used, the reference voltage should be buffered externally by connecting a small (approximately 1 nF) capacitor to the VREFBG pin to reduce the noise on the reference.

The CTSD16 has a fixed 1.024-MHz clock (f_M). Fault flags for this oscillator are described in the CTSD16 and UCS section of the MSP430F5xx and MSP430F6xx Family User's Guide.

Rail-to-rail operation mode is available when the OA module is used to buffer the CTSD16 inputs. For more information, see the CTSD16 and the OA modules in the MSP430F5xx and MSP430F6xx Family User's Guide.