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ZHCSDF2E October 2014 – December 2019 MSP430FR2032 , MSP430FR2033

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PM|64
- MTQF008B
DGG|48
- MPDS583
DGG|56
- MPDS570

散热焊盘机械数据 (封装 | 引脚)

订购信息

Table 5-14 eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 1, UCMODEx = 01 or 10		1		UCxCLK cycles
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 1, UCMODEx = 01 or 10		1		UCxCLK cycles
t_SU,MI	SOMI input data setup time		2 V	45		ns
t_SU,MI	SOMI input data setup time		3 V	35		ns
t_HD,MI	SOMI input data hold time		2 V	0		ns
t_HD,MI	SOMI input data hold time		3 V	0		ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2 V		20	ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3 V		20	ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	2 V	0		ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	3 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)})
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-9 and Figure 5-10.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-9 and Figure 5-10.

MSP430FR2033 MSP430FR2032 slas639-eUSCI_master_CKPH0.gif

Figure 5-9 SPI Master Mode, CKPH = 0

MSP430FR2033 MSP430FR2032 slas639-eUSCI_master_CKPH1.gif

Figure 5-10 SPI Master Mode, CKPH = 1