ZHCSDF2E October   2014  – December 2019 MSP430FR2032 , MSP430FR2033

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics - Current Consumption Per Module
    11. 5.11 Thermal Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2 Reset Timing
        1. Table 5-2 Wake-Up Times From Low-Power Modes and Reset
      3. 5.12.3 Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 REFO
        4. Table 5-6 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-7 Module Oscillator Clock (MODCLK)
      4. 5.12.4 Digital I/Os
        1. Table 5-8 Digital Inputs
        2. Table 5-9 Digital Outputs
        3. 5.12.4.1  Digital I/O Typical Characteristics
      5. 5.12.5 Timer_A
        1. Table 5-10 Timer_A Recommended Operating Conditions
      6. 5.12.6 eUSCI
        1. Table 5-11 eUSCI (UART Mode) Recommended Operating Conditions
        2. Table 5-12 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-13 eUSCI (SPI Master Mode) Recommended Operating Conditions
        4. Table 5-14 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-15 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-16 eUSCI (I2C Mode) Switching Characteristics
      7. 5.12.7 ADC
        1. Table 5-17 ADC, Power Supply and Input Range Conditions
        2. Table 5-18 ADC, 10-Bit Timing Parameters
        3. Table 5-19 ADC, 10-Bit Linearity Parameters
      8. 5.12.8 FRAM
        1. Table 5-20 FRAM
      9. 5.12.9 Emulation and Debug
        1. Table 5-21 JTAG and Spy-Bi-Wire Interface Characteristics
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Bootloader (BSL)
    5. 6.5  JTAG Standard Interface
    6. 6.6  Spy-Bi-Wire Interface (SBW)
    7. 6.7  FRAM
    8. 6.8  Memory Protection
    9. 6.9  Peripherals
      1. 6.9.1  Power Management Module (PMM) and On-chip Reference Voltages
      2. 6.9.2  Clock System (CS) and Clock Distribution
      3. 6.9.3  General-Purpose Input/Output Port (I/O)
      4. 6.9.4  Watchdog Timer (WDT)
      5. 6.9.5  System Module (SYS)
      6. 6.9.6  Cyclic Redundancy Check (CRC)
      7. 6.9.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.9.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.9.9  Real-Time Clock (RTC) Counter
      10. 6.9.10 10-Bit Analog Digital Converter (ADC)
      11. 6.9.11 Embedded Emulation Module (EEM)
      12. 6.9.12 Input/Output Diagrams
        1. 6.9.12.1  Port P1 Input/Output With Schmitt Trigger
        2. 6.9.12.2  Port P2 Input/Output With Schmitt Trigger
        3. 6.9.12.3  Port P3 Input/Output With Schmitt Trigger
        4. 6.9.12.4  Port P4.0 Input/Output With Schmitt Trigger
        5. 6.9.12.5  Port P4.1 and P4.2 Input/Output With Schmitt Trigger
        6. 6.9.12.6  Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
        7. 6.9.12.7  Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
        8. 6.9.12.8  Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
        9. 6.9.12.9  Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
        10. 6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
        11. 6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
        12. 6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
        13. 6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
        14. 6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
    10. 6.10 Device Descriptors (TLV)
    11. 6.11 Memory
      1. 6.11.1 Peripheral File Map
    12. 6.12 Identification
      1. 6.12.1 Revision Identification
      2. 6.12.2 Device Identification
      3. 6.12.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 开始使用
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 社区资源
    7. 8.7 商标
    8. 8.8 静电放电警告
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.9.8 Timers (Timer0_A3, Timer1_A3)

The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers each. Each timer can support multiple captures or compares, PWM outputs, and interval timing. Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are not externally connected and can only be used for hardware period timing and interrupt generation. In Up mode, they can be used to set the overflow value of the counter.

Table 6-10 Timer0_A3 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P1.5 TA0CLK TACLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
From Capacitive Touch I/O (internal) INCLK
CCI0A CCR0 TA0
CCI0B Timer1_A3 CCI0B input
DVSS GND
DVCC VCC
P1.7 TA0.1 CCI1A CCR1 TA1 TA0.1
From RTC (internal) CCI1B Timer1_A3 CCI1B input
DVSS GND
DVCC VCC
P1.6 TA0.2 CCI2A CCR2 TA2 TA0.2
From Capacitive Touch I/O (internal) CCI2B Timer1_A3 INCLK
Timer1_A3 CCI2B input,
IR Input
DVSS GND
DVCC VCC

Table 6-11 Timer1_A3 Signal Connections

PORT PIN DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
P8.2 TA1CLK TACLK Timer N/A
ACLK (internal) ACLK
SMCLK (internal) SMCLK
Timer0_A3 CCR2B output (internal) INCLK
CCI0A CCR0 TA0
Timer0_A3 CCR0B output (internal) CCI0B
DVSS GND
DVCC VCC
P4.0 TA1.1 CCI1A CCR1 TA1 TA1.1
Timer0_A3 CCR1B output (internal) CCI1B To ADC trigger
DVSS GND
DVCC VCC
P8.3 TA1.2 CCI2A CCR2 TA2 TA1.2
Timer0_A3 CCR2B output (internal) CCI2B IR Input
DVSS GND
DVCC VCC

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or FSK mode. This configuration helps an application easily acquire a modulated infrared command for directly driving an external IR diode.

The IR functions are controlled by the following bits in the System Configuration 1 (SYSCFG1) register: IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data). For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.
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