ZHCSEA0F October   2015  – December 2019 MSP430FR2433

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics - Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.11.6  Timer_A
        1. Table 5-13 Timer_A
      7. 5.11.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode)
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode)
        5. Table 5-18 eUSCI (SPI Slave Mode)
        6. Table 5-19 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.11.9  FRAM
        1. Table 5-23 FRAM
      10. 5.11.10 Debug and Emulation
        1. Table 5-24 JTAG, Spy-Bi-Wire Interface
        2. Table 5-25 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      3. 6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和后续步骤
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 社区资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.4 功能方框图

Figure 1-1 给出了功能方框图。

MSP430FR2433 msp430fr2433-functional-block-diagram.gifFigure 1-1 功能框图
  • MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为 4.7μF 至 10μF 和 0.1μF，精度为 ±5%。
  • P1 和 P2 特有引脚中断功能，可将 MCU 从所有 LPM 唤醒（包括 LPM3.5 和 LPM4）。
  • 每个 Timer_A3 具有 3 个捕捉/比较寄存器，不过仅 CCR1 和 CCR2 从外部连接。CCR0 寄存器仅用于内部周期时序和生成中断。
  • 每个 Timer_A2 具有两个捕捉/比较寄存器，仅 CCR1 具有比较/捕捉功能。CCR0 寄存器仅用于内部周期时序和生成中断。
  • 在 LPM3.5 模式下，RTC 模块可在其他外设停止工作的情况下继续工作。
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