ZHCSDF6F October 2014 – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133
PRODUCTION DATA
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers each. Each can support multiple captures or compares, PWM outputs, and interval timing. Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are not externally connected and can only be used for hardware period timing and interrupt generation. In Up Mode, they can be used to set the overflow value of the counter.
| PORT PIN | DEVICE INPUT SIGNAL | MODULE INPUT NAME | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL |
|---|---|---|---|---|---|
| P1.5 | TA0CLK | TACLK | Timer | N/A | |
| ACLK (internal) | ACLK | ||||
| SMCLK (internal) | SMCLK | ||||
| from Capacitive Touch IO (internal) | INCLK | ||||
| CCI0A | CCR0 | TA0 | |||
| CCI0B | Timer1_A3 CCI0B input | ||||
| DVSS | GND | ||||
| DVCC | VCC | ||||
| P1.7 | TA0.1 | CCI1A | CCR1 | TA1 | TA0.1 |
| from RTC (internal) | CCI1B | Timer1_A3 CCI1B input | |||
| DVSS | GND | ||||
| DVCC | VCC | ||||
| P1.6 | TA0.2 | CCI2A | CCR2 | TA2 | TA0.2 |
| from Capacitive Touch I/O (internal) | CCI2B | Timer1_A3 INCLK Timer1_A3 CCI2B input, IR Input | |||
| DVSS | GND | ||||
| DVCC | VCC |
| PORT PIN | DEVICE INPUT SIGNAL | MODULE INPUT NAME | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL |
|---|---|---|---|---|---|
| P8.2 | TA1CLK | TACLK | Timer | N/A | |
| ACLK (internal) | ACLK | ||||
| SMCLK (internal) | SMCLK | ||||
| Timer0_A3 CCR2B output (internal) | INCLK | ||||
| CCI0A | CCR0 | TA0 | |||
| Timer0_A3 CCR0B output (internal) | CCI0B | ||||
| DVSS | GND | ||||
| DVCC | VCC | ||||
| P4.0 | TA1.1 | CCI1A | CCR1 | TA1 | TA1.1 |
| Timer0_A3 CCR1B output (internal) | CCI1B | to ADC trigger | |||
| DVSS | GND | ||||
| DVCC | VCC | ||||
| P8.3 | TA1.2 | CCI2A | CCR2 | TA2 | TA1.2 |
| Timer0_A3 CCR2B output (internal) | CCI2B | IR Input | |||
| DVSS | GND | ||||
| DVCC | VCC |
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for directly driving an external IR diode. The IR functions are fully controlled by SYS configuration registers 1 including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA (data) bits. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide.