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ZHCSDF6F October 2014 – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

PRODUCTION DATA

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机械数据 (封装 | 引脚)

PM|64
- MTQF008B
DGG|48
- MPDS583
DGG|56
- MPDS570

散热焊盘机械数据 (封装 | 引脚)

订购信息

9.9.2 Clock System (CS) and Clock Distribution

The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock (MODCLK). The clock system is designed to target cost-effective designs with minimal external components. A fail-safe mechanism is designed for XT1. The clock system module offers the following clock signals.

Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the bus. All clock sources except MODCLK can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or 128.
Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to 40 kHz.

All peripherals may have one or several clock sources depending on specific functionality. Table 9-6 shows the clock distribution used in this device.

Table 9-6 Clock Distribution

	CLOCK SOURCE SELECT BITS	MCLK	SMCLK	ACLK	MODCLK	XT1CLK⁽¹⁾	VLOCLK	EXTERNAL PIN
Frequency Range		DC to 16 MHz	DC to 16 MHz	DC to 40 kHz	5 MHz ±10%	DC to 40 kHz	10 kHz ±50%
CPU	N/A	Default
FRAM	N/A	Default
RAM	N/A	Default
CRC	N/A	Default
I/O	N/A	Default
TA0	TASSEL		10b	01b				00b (TA0CLK pin)
TA1	TASSEL		10b	01b				00b (TA1CLK pin)
eUSCI_A0	UCSSELx		10b or 11b		01b			00b (UCA0CLK pin)
eUSCI_B0	UCSSELx		10b or 11b		01b			00b (UCB0CLK pin)
WDT	WDTSSEL		00b	01b			10b
ADC	ADCSSEL		10b or 11b	01b	00b
LCD	LCDSSEL			01b		00b	10b
RTC	RTCSS		01b			10b	11b

(1) To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.

Figure 9-1 Clock Distribution Block Diagram