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ZHCSDF6F October 2014 – December 2021 MSP430FR4131 , MSP430FR4132 , MSP430FR4133

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PM|64
- MTQF008B
DGG|48
- MPDS583
DGG|56
- MPDS570

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8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 1, UCMODEx = 01 or 10		1		UCxCLK cycles
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 1, UCMODEx = 01 or 10		1		UCxCLK cycles
t_SU,MI	SOMI input data setup time		2 V	45		ns
t_SU,MI	SOMI input data setup time		3 V	35		ns
t_HD,MI	SOMI input data hold time		2 V	0		ns
t_HD,MI	SOMI input data hold time		3 V	0		ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2 V		20	ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3 V		20	ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	2 V	0		ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	3 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)})
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-10 and Figure 8-11.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 8-10 and Figure 8-11.

Figure 8-10 SPI Master Mode, CKPH = 0

Figure 8-11 SPI Master Mode, CKPH = 1

Section 8.12.6.5 lists the switching characteristics of the eUSCI in SPI slave mode.