ZHCSJA6B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VR+ | Positive external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit | VR+ > VR– | 1.2 | AVCC | V | |
VR– | Negative external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit | VR+ > VR– | 0 | 1.2 | V | |
VR+ – VR– | Differential external reference voltage input | VR+ > VR– | 1.2 | AVCC | V | |
IVeREF+, IVeREF- | Static input current singled-ended input mode | 1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 0, ADC12PWRMD = 0 | ±10 | µA | ||
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 0, ADC12PWRMD = 01 | ±2.5 | µA | ||||
IVeREF+, IVeREF- | Static input current differential input mode | 1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 1, ADC12PWRMD = 0 | ±20 | µA | ||
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V fADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 1, ADC12PWRMD = 1 | ±5 | µA | ||||
IVeREF+ | Peak input current with single-ended input | 0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0 | 1.5 | mA | ||
IVeREF+ | Peak input current with differential input | 0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1 | 3 | mA | ||
CVeREF+/- | Capacitance at VeREF+ or VeREF- terminal | See (2) | 10 | µF |