米6体育平台手机版

ZHCSCG3C May 2014 – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RHA|40
- MPQF135D

散热焊盘机械数据 (封装 | 引脚)

RHA|40
- QFND027R

订购信息

6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-1 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power-Up, Brownout, Supply Supervisors External Reset RST Watchdog Time-out (Watchdog mode) WDT, FRCTL MPU, CS, PMM Password Violation FRAM double bit error detection MPU segment violation Software POR, BOR	SVSLIFG, SVSHIFG PMMRSTIFG WDTIFG WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW DBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG PMMPORIFG, PMMBORIFG (SYSRSTIV) ⁽¹⁾⁽³⁾	Reset	0FFFEh	63, highest
System NMI Vacant Memory Access JTAG Mailbox FRAM access time error FRAM single, double bit error detection	VMAIFG JMBNIFG, JMBOUTIFG ACCTIMIFG SBDIFG, DBDIFG (SYSSNIV) ⁽¹⁾	(Non)maskable	0FFFCh	62
User NMI External NMI Oscillator Fault	NMIIFG, OFIFG (SYSUNIV) ⁽¹⁾⁽³⁾	(Non)maskable	0FFFAh	61
Comparator_D	Comparator_D interrupt flags (CBIV) ⁽¹⁾⁽²⁾	Maskable	0FFF8h	60
TB0	TB0CCR0 CCIFG0 ⁽²⁾	Maskable	0FFF6h	59
TB0	TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2, TB0IFG (TB0IV) ⁽¹⁾⁽²⁾	Maskable	0FFF4h	58
Watchdog Timer (Interval Timer Mode)	WDTIFG	Maskable	0FFF2h	57
eUSCI_A0 Receive and Transmit	UCA0RXIFG, UCA0TXIFG (SPI mode) UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG, UXA0TXIFG (UART mode) (UCA0IV) ⁽¹⁾⁽²⁾	Maskable	0FFF0h	56
eUSCI_B0 Receive and Transmit	UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG, UCB0TXIFG (SPI mode) UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG, UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0, UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2, UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3, UCB0CNTIFG, UCB0BIT9IFG (I²C mode) (UCB0IV) ⁽¹⁾⁽²⁾	Maskable	0FFEEh	55
ADC10_B	ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG, ADC10LOIFG ADC10INIFG, ADC10IFG0 (ADC10IV) ⁽¹⁾⁽²⁾⁽⁵⁾	Maskable	0FFECh	54
TA0	TA0CCR0 CCIFG0 ⁽²⁾	Maskable	0FFEAh	53
TA0	TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2, TA0IFG (TA0IV) ⁽¹⁾⁽²⁾	Maskable	0FFE8h	52
eUSCI_A1 Receive and Transmit	UCA1RXIFG, UCA1TXIFG (SPI mode) UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG, UXA1TXIFG (UART mode) (UCA1IV) ⁽¹⁾⁽²⁾	Maskable	0FFE6h	51
DMA	DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) ⁽¹⁾⁽²⁾	Maskable	0FFE4h	50
TA1	TA1CCR0 CCIFG0 ⁽²⁾	Maskable	0FFE2h	49
TA1	TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) ⁽¹⁾⁽²⁾	Maskable	0FFE0h	48
I/O Port P1	P1IFG.0 to P1IFG.7 (P1IV) ⁽¹⁾⁽²⁾	Maskable	0FFDEh	47
TB1	TB1CCR0 CCIFG0 ⁽²⁾	Maskable	0FFDCh	46
TB1	TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2, TB1IFG (TB1IV) ⁽¹⁾⁽²⁾	Maskable	0FFDAh	45
I/O Port P2	P2IFG.0 to P2IFG.7 (P2IV) ⁽¹⁾⁽²⁾	Maskable	0FFD8h	44
TB2	TB2CCR0 CCIFG0 ⁽²⁾	Maskable	0FFD6h	43
TB2	TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2, TB2IFG (TB2IV) ⁽¹⁾⁽²⁾	Maskable	0FFD4h	42
I/O Port P3	P3IFG.0 to P3IFG.7 (P3IV) ⁽¹⁾⁽²⁾	Maskable	0FFD2h	41
I/O Port P4	P4IFG.0 to P4IFG.2 (P4IV) ⁽¹⁾⁽²⁾	Maskable	0FFD0h	40
RTC_B	RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) ⁽¹⁾⁽²⁾	Maskable	0FFCEh	39
Reserved	Reserved ⁽⁴⁾		0FFCCh	38
			⋮	⋮
			0FF80h	0, lowest

(1) Multiple source flags

(2) Interrupt flags are located in the module.

(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, it is recommended to reserve these locations.

(5) Only on devices with ADC, otherwise reserved.