ZHCSCG3C May   2014  – December 2017 MSP430FR5720 , MSP430FR5721 , MSP430FR5722 , MSP430FR5723 , MSP430FR5724 , MSP430FR5725 , MSP430FR5726 , MSP430FR5727 , MSP430FR5728 , MSP430FR5729

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3.     4
    4. 1.3 说明
    5. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram – RHA Package – MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
    2. 4.2 Pin Diagram – DA Package – MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
    3. 4.3 Pin Diagram – RGE Package – MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
    4. 4.4 Pin Diagram – PW Package – MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
    5. 4.5 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    11. 5.11 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
    12. 5.12 Typical Characteristics – Outputs
    13. 5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
    14. 5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
    15. 5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    16. 5.16 DCO Frequencies
    17. 5.17 MODOSC
    18. 5.18 PMM, Core Voltage
    19. 5.19 PMM, SVS, BOR
    20. 5.20 Wake-up Times From Low-Power Modes
    21. 5.21 Timer_A
    22. 5.22 Timer_B
    23. 5.23 eUSCI (UART Mode) Clock Frequency
    24. 5.24 eUSCI (UART Mode)
    25. 5.25 eUSCI (SPI Master Mode) Clock Frequency
    26. 5.26 eUSCI (SPI Master Mode)
    27. 5.27 eUSCI (SPI Slave Mode)
    28. 5.28 eUSCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions
    30. 5.30 10-Bit ADC, Timing Parameters
    31. 5.31 10-Bit ADC, Linearity Parameters
    32. 5.32 REF, External Reference
    33. 5.33 REF, Built-In Reference
    34. 5.34 REF, Temperature Sensor and Built-In VMID
    35. 5.35 Comparator_D
    36. 5.36 FRAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit (MPU)
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TB0, TB1, TB2
      12. 6.10.12 ADC10_B
      13. 6.10.13 Comparator_D
      14. 6.10.14 CRC16
      15. 6.10.15 Shared Reference (REF)
      16. 6.10.16 Embedded Emulation Module (EEM)
      17. 6.10.17 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.7) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
      10. 6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
      12. 6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
      13. 6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      14. 6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
  7. 7器件和文档支持
    1. 7.1  开始使用
    2. 7.2  Device Nomenclature
    3. 7.3  工具和软件
    4. 7.4  文档支持
    5. 7.5  相关链接
    6. 7.6  社区资源
    7. 7.7  商标
    8. 7.8  静电放电警告
    9. 7.9  出口管制提示
    10. 7.10 术语表
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.10.8 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-7 lists all triggers to start DMA transfers.

Table 6-7 DMA Trigger Assignments (1)

TRIGGERCHANNEL 0CHANNEL 1CHANNEL 2
0 DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG
3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG
4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG
5 Reserved Reserved Reserved
6 Reserved Reserved Reserved
7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG
8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG
9 TB1CCR0 CCIFG (3) TB1CCR0 CCIFG (3) TB1CCR0 CCIFG (3)
10 TB1CCR2 CCIFG (3) TB1CCR2 CCIFG (3) TB1CCR2 CCIFG (3)
11 TB2CCR0 CCIFG (4) TB2CCR0 CCIFG (4) TB2CCR0 CCIFG (4)
12 TB2CCR2 CCIFG (4) TB2CCR2 CCIFG (4) TB2CCR2 CCIFG (4)
13 Reserved Reserved Reserved
14 UCA0RXIFG UCA0RXIFG UCA0RXIFG
15 UCA0TXIFG UCA0TXIFG UCA0TXIFG
16 UCA1RXIFG (5) UCA1RXIFG (5) UCA1RXIFG (5)
17 UCA1TXIFG (5) UCA1TXIFG (5) UCA1TXIFG (5)
18 UCB0RXIFG0 UCB0RXIFG0 UCB0RXIFG0
19 UCB0TXIFG0 UCB0TXIFG0 UCB0TXIFG0
20 UCB0RXIFG1 UCB0RXIFG1 UCB0RXIFG1
21 UCB0TXIFG1 UCB0TXIFG1 UCB0TXIFG1
22 UCB0RXIFG2 UCB0RXIFG2 UCB0RXIFG2
23 UCB0TXIFG2 UCB0TXIFG2 UCB0TXIFG2
24 UCB0RXIFG3 UCB0RXIFG3 UCB0RXIFG3
25 UCB0TXIFG3 UCB0TXIFG3 UCB0TXIFG3
26 ADC10IFGx (2) ADC10IFGx (2) ADC10IFGx (2)
27 Reserved Reserved Reserved
28 Reserved Reserved Reserved
29 MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 DMAE0 DMAE0 DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with ADC, otherwise reserved
(3) Only on devices with TB1, otherwise reserved
(4) Only on devices with TB2, otherwise reserved
(5) Only on devices with eUSCI_A1, otherwise reserved
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