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ZHCS180L July 2011 – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

RGE|24
- MPQF124G
PW|28
- MPDS364

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND024AD

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5.4 Active Mode Supply Current Into V_CC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

PARAMETER	EXECUTION MEMORY	V_CC	Frequency (f_MCLK = f_SMCLK)⁽⁵⁾												UNIT
			1 MHz		4 MHz		8 MHz		16 MHz		20 MHz		24 MHz
			TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX	TYP	MAX
I_{AM, FRAM_UNI}⁽⁶⁾	FRAM	3 V	0.27		0.58		1.0		1.53		1.9		2.2		mA
I_AM,0%⁽⁷⁾	FRAM 0% cache hit ratio	3 V	0.42	0.73	1.2	1.6	2.2	2.8	2.3	2.9	2.8	3.6	3.45	4.3	mA
I_AM,50%⁽⁷⁾⁽⁴⁾	FRAM 50% cache hit ratio	3 V	0.31		0.73		1.3		1.75		2.1		2.5		mA
I_AM,66%⁽⁷⁾⁽⁴⁾	FRAM 66% cache hit ratio	3 V	0.27		0.58		1.0		1.55		1.9		2.2		mA
I_AM,75%⁽⁷⁾⁽⁴⁾	FRAM 75% cache hit ratio	3 V	0.25		0.5		0.82		1.3		1.6		1.8		mA
I_AM,100%⁽⁷⁾⁽⁴⁾	FRAM 100% cache hit ratio	3 V	0.2	0.43	0.3	0.55	0.42	0.8	0.73	1.15	0.88	1.3	1.0	1.5	mA
I_{AM, RAM}⁽⁴⁾⁽⁸⁾	RAM	3 V	0.2	0.4	0.35	0.55	0.55	0.75	1.0	1.25	1.20	1.45	1.45	1.75	mA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.

(3) Characterized with program executing typical data processing.

(4) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in Section 5.4.
f_ACLK = 32786 Hz, f_MCLK = f_SMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

(5) At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency, f_MCLK,eff, decreases. The effective MCLK frequency is also dependent on the cache hit ratio. SMCLK is not affected by the number of wait states or the cache hit ratio. The following equation can be used to compute f_MCLK,eff:
f_MCLK,eff,MHZ = f_MCLK,MHZ × 1 / [number of wait states × ((1 – cache hit ratio percent/100)) + 1]

(6) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK.

(7) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (f_DCO = 16 MHz).MCLK = SMCLK. One wait state enabled.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (f_DCO = 20 MHz).MCLK = SMCLK. Three wait states enabled.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (f_DCO = 24 MHz).MCLK = SMCLK. Three wait states enabled.

(8) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (f_DCO = 8 MHz). MCLK = SMCLK.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (f_DCO = 16 MHz). MCLK = SMCLK.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (f_DCO = 20 MHz). MCLK = SMCLK.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (f_DCO = 24 MHz). MCLK = SMCLK.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639_IAM_nowait_curves.gif

Figure 5-1 Typical Active Mode Supply Currents, No Wait States

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机械数据 (封装 | 引脚)

散热焊盘机械数据 (封装 | 引脚)

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5.4 Active Mode Supply Current Into VCC Excluding External Current

5.4 Active Mode Supply Current Into V_CC Excluding External Current