ZHCS180L July 2011 – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739
PRODUCTION DATA.
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE | INTERRUPT FLAG | SYSTEM INTERRUPT | WORD ADDRESS | PRIORITY |
---|---|---|---|---|
System Reset Power-Up, Brownout, Supply Supervisors External Reset RST Watchdog Time-out (Watchdog mode) WDT, FRCTL MPU, CS, PMM Password Violation FRAM double bit error detection MPU segment violation Software POR, BOR |
SVSLIFG, SVSHIFG PMMRSTIFG WDTIFG WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW DBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG PMMPORIFG, PMMBORIFG (SYSRSTIV) (1)(3) |
Reset | 0FFFEh | 63, highest |
System NMI Vacant Memory Access JTAG Mailbox FRAM access time error FRAM single, double bit error detection |
VMAIFG JMBNIFG, JMBOUTIFG ACCTIMIFG SBDIFG, DBDIFG (SYSSNIV) (1) |
(Non)maskable | 0FFFCh | 62 |
User NMI External NMI Oscillator Fault |
NMIIFG, OFIFG (SYSUNIV) (1)(3) |
(Non)maskable | 0FFFAh | 61 |
Comparator_D | Comparator_D interrupt flags (CBIV) (1)(2) |
Maskable | 0FFF8h | 60 |
TB0 | TB0CCR0 CCIFG0 (2) | Maskable | 0FFF6h | 59 |
TB0 | TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2, TB0IFG (TB0IV) (1)(2) |
Maskable | 0FFF4h | 58 |
Watchdog Timer (Interval Timer Mode) |
WDTIFG | Maskable | 0FFF2h | 57 |
eUSCI_A0 Receive and Transmit | UCA0RXIFG, UCA0TXIFG (SPI mode) UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG, UXA0TXIFG (UART mode) (UCA0IV) (1)(2) |
Maskable | 0FFF0h | 56 |
eUSCI_B0 Receive and Transmit | UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG, UCB0TXIFG (SPI mode) UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG, UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0, UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2, UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3, UCB0CNTIFG, UCB0BIT9IFG (I2C mode) (UCB0IV) (1)(2) |
Maskable | 0FFEEh | 55 |
ADC10_B | ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG, ADC10LOIFG ADC10INIFG, ADC10IFG0 (ADC10IV) (1)(2)(5) |
Maskable | 0FFECh | 54 |
TA0 | TA0CCR0 CCIFG0 (2) | Maskable | 0FFEAh | 53 |
TA0 | TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2, TA0IFG (TA0IV) (1)(2) |
Maskable | 0FFE8h | 52 |
eUSCI_A1 Receive and Transmit | UCA1RXIFG, UCA1TXIFG (SPI mode) UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG, UXA1TXIFG (UART mode) (UCA1IV) (1)(2) |
Maskable | 0FFE6h | 51 |
DMA | DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1)(2) |
Maskable | 0FFE4h | 50 |
TA1 | TA1CCR0 CCIFG0 (2) | Maskable | 0FFE2h | 49 |
TA1 | TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV) (1)(2) |
Maskable | 0FFE0h | 48 |
I/O Port P1 | P1IFG.0 to P1IFG.7 (P1IV) (1)(2) |
Maskable | 0FFDEh | 47 |
TB1 | TB1CCR0 CCIFG0 (2) | Maskable | 0FFDCh | 46 |
TB1 | TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2, TB1IFG (TB1IV) (1)(2) |
Maskable | 0FFDAh | 45 |
I/O Port P2 | P2IFG.0 to P2IFG.7 (P2IV) (1)(2) |
Maskable | 0FFD8h | 44 |
TB2 | TB2CCR0 CCIFG0 (2) | Maskable | 0FFD6h | 43 |
TB2 | TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2, TB2IFG (TB2IV) (1)(2) |
Maskable | 0FFD4h | 42 |
I/O Port P3 | P3IFG.0 to P3IFG.7 (P3IV) (1)(2) |
Maskable | 0FFD2h | 41 |
I/O Port P4 | P4IFG.0 to P4IFG.2 (P4IV) (1)(2) |
Maskable | 0FFD0h | 40 |
RTC_B | RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) (1)(2) |
Maskable | 0FFCEh | 39 |
Reserved | Reserved (4) | 0FFCCh | 38 | |
⋮ | ⋮ | |||
0FF80h | 0, lowest |