米6体育平台手机版

ZHCS180L July 2011 – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

YQD|24
- MXBG304A
RGE|24
- MPQF124G
PW|28
- MPDS364

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND024AD

订购信息

5.26 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V	1		UCxCLK cycles
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V		55	ns
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V		35	ns
t_STE,DIS	STE disable time, STE inactive to SIMO high impedance	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SIMO high impedance	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V		30	ns
t_SU,MI	SOMI input data setup time		2 V	35		ns
t_SU,MI	SOMI input data setup time		3 V	35		ns
t_HD,MI	SOMI input data hold time		2 V	0		ns
t_HD,MI	SOMI input data hold time		3 V	0		ns
t_VALID,MO	SIMO output data valid time ⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2 V		30	ns
t_VALID,MO	SIMO output data valid time ⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3 V		30	ns
t_HD,MO	SIMO output data hold time ⁽³⁾	C_L = 20 pF	2 V	0		ns
t_HD,MO	SIMO output data hold time ⁽³⁾	C_L = 20 pF	3 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-6 and Figure 5-7.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-6 and Figure 5-7.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-eUSCI_master_CKPH0.gif

Figure 5-6 SPI Master Mode, CKPH = 0

Figure 5-7 SPI Master Mode, CKPH = 1