米6体育平台手机版

ZHCS180L July 2011 – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

YQD|24
- MXBG304A
RGE|24
- MPQF124G
PW|28
- MPDS364

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND024AD

订购信息

5.27 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock		2 V	7		ns
t_STE,LEAD	STE lead time, STE active to clock		3 V	7		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		2 V	0		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		3 V	0		ns
t_STE,ACC	STE access time, STE active to SOMI data out		2 V		65	ns
t_STE,ACC	STE access time, STE active to SOMI data out		3 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		2 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		3 V		35	ns
t_SU,SI	SIMO input data setup time		2 V	2		ns
t_SU,SI	SIMO input data setup time		3 V	2		ns
t_HD,SI	SIMO input data hold time		2 V	5		ns
t_HD,SI	SIMO input data hold time		3 V	5		ns
t_VALID,SO	SOMI output data valid time ⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2 V		30	ns
t_VALID,SO	SOMI output data valid time ⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3 V		30	ns
t_HD,SO	SOMI output data hold time ⁽³⁾	C_L = 20 pF	2 V	4		ns
t_HD,SO	SOMI output data hold time ⁽³⁾	C_L = 20 pF	3 V	4		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8 and Figure 5-9.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-8 and Figure 5-9.

MSP430FR5739 MSP430FR5738 MSP430FR5737 MSP430FR5736 MSP430FR5735 MSP430FR5734 MSP430FR5733 MSP430FR5732 MSP430FR5731 MSP430FR5730 slas639-eUSCI_slave_CKPH0.gif

Figure 5-8 SPI Slave Mode, CKPH = 0

Figure 5-9 SPI Slave Mode, CKPH = 1