ZHCS180L July 2011 – December 2017 MSP430FR5730 , MSP430FR5731 , MSP430FR5732 , MSP430FR5733 , MSP430FR5734 , MSP430FR5735 , MSP430FR5736 , MSP430FR5737 , MSP430FR5738 , MSP430FR5739
PRODUCTION DATA.
- 1器件概述
- 2修订历史记录
- 3Device Comparison
-
4Terminal Configuration and Functions
- 4.1 Pin Diagram – RHA Package – MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
- 4.2 Pin Diagram – DA Package – MSP430FR5731, MSP430FR5733, MSP430FR5735, MSP430FR5737, MSP430FR5739
- 4.3 Pin Diagram – RGE Package – MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
- 4.4 Pin Diagram – YQD Package – MSP430FR5738
- 4.5 Pin Diagram – PW Package – MSP430FR5730, MSP430FR5732, MSP430FR5734, MSP430FR5736, MSP430FR5738
- 4.6 Signal Descriptions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Active Mode Supply Current Into VCC Excluding External Current
- 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 5.6 Thermal Resistance Characteristics
- 5.7 Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
- 5.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- 5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
- 5.10 Outputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
- 5.11 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
- 5.12 Typical Characteristics – Outputs
- 5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
- 5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
- 5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 5.16 DCO Frequencies
- 5.17 MODOSC
- 5.18 PMM, Core Voltage
- 5.19 PMM, SVS, BOR
- 5.20 Wake-up Times From Low-Power Modes
- 5.21 Timer_A
- 5.22 Timer_B
- 5.23 eUSCI (UART Mode) Clock Frequency
- 5.24 eUSCI (UART Mode)
- 5.25 eUSCI (SPI Master Mode) Clock Frequency
- 5.26 eUSCI (SPI Master Mode)
- 5.27 eUSCI (SPI Slave Mode)
- 5.28 eUSCI (I2C Mode)
- 5.29 10-Bit ADC, Power Supply and Input Range Conditions
- 5.30 10-Bit ADC, Timing Parameters
- 5.31 10-Bit ADC, Linearity Parameters
- 5.32 REF, External Reference
- 5.33 REF, Built-In Reference
- 5.34 REF, Temperature Sensor and Built-In VMID
- 5.35 Comparator_D
- 5.36 FRAM
- 5.37 JTAG and Spy-Bi-Wire Interface
-
6Detailed Description
- 6.1 Functional Block Diagrams
- 6.2 CPU
- 6.3 Operating Modes
- 6.4 Interrupt Vector Addresses
- 6.5 Memory Organization
- 6.6 Bootloader (BSL)
- 6.7 JTAG Operation
- 6.8 FRAM
- 6.9 Memory Protection Unit (MPU)
- 6.10
Peripherals
- 6.10.1 Digital I/O
- 6.10.2 Oscillator and Clock System (CS)
- 6.10.3 Power-Management Module (PMM)
- 6.10.4 Hardware Multiplier (MPY)
- 6.10.5 Real-Time Clock (RTC_B)
- 6.10.6 Watchdog Timer (WDT_A)
- 6.10.7 System Module (SYS)
- 6.10.8 DMA Controller
- 6.10.9 Enhanced Universal Serial Communication Interface (eUSCI)
- 6.10.10 TA0, TA1
- 6.10.11 TB0, TB1, TB2
- 6.10.12 ADC10_B
- 6.10.13 Comparator_D
- 6.10.14 CRC16
- 6.10.15 Shared Reference (REF)
- 6.10.16 Embedded Emulation Module (EEM)
- 6.10.17 Peripheral File Map
- 6.11
Input/Output Diagrams
- 6.11.1 Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
- 6.11.2 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
- 6.11.3 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
- 6.11.4 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
- 6.11.5 Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
- 6.11.6 Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
- 6.11.7 Port P2 (P2.7) Input/Output With Schmitt Trigger
- 6.11.8 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
- 6.11.9 Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
- 6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
- 6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
- 6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
- 6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
- 6.12 Device Descriptors (TLV)
- 7器件和文档支持
- 8机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- RGE|24
订购信息
6.11.1 Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
Figure 6-9 shows the port diagram. Table 6-39 summarizes the selection of the pin functions.
Table 6-39 Port P1 (P1.0 to P1.2) Pin Functions
| PIN NAME (P1.x) | x | FUNCTION | CONTROL BITS OR SIGNALS | ||
|---|---|---|---|---|---|
| P1DIR.x | P1SEL1.x | P1SEL0.x | |||
| P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF- | 0 | P1.0 (I/O) | I: 0; O: 1 | 0 | 0 |
| TA0.CCI1A | 0 | 0 | 1 | ||
| TA0.1 | 1 | ||||
| DMAE0 | 0 | 1 | 0 | ||
| RTCCLK | 1 | ||||
| A0 (1)(3) CD0 (1)(2) VeREF- (1)(3) |
X | 1 | 1 | ||
| P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+ | 1 | P1.1 (I/O) | I: 0; O: 1 | 0 | 0 |
| TA0.CCI2A | 0 | 0 | 1 | ||
| TA0.2 | 1 | ||||
| TA1CLK | 0 | 1 | 0 | ||
| CDOUT | 1 | ||||
| A1 (1)(3) CD1 (1)(2) VeREF+ (1)(3) |
X | 1 | 1 | ||
| P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2 | 2 | P1.2 (I/O) | I: 0; O: 1 | 0 | 0 |
| TA1.CCI1A | 0 | 0 | 1 | ||
| TA1.1 | 1 | ||||
| TA0CLK | 0 | 1 | 0 | ||
| CDOUT | 1 | ||||
| A2 (1)(3) CD2 (1)(2) |
X | 1 | 1 | ||
(1) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
(2) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
(3) Not available on all devices and package types.