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ZHCSCH3G October 2012 – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DA|38
- MPDS502
RHA|40
- MPQF135D

散热焊盘机械数据 (封装 | 引脚)

DA|38
- QFND327
RHA|40
- QFND047R

订购信息

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison⁽⁷⁾⁽⁸⁾

DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	ADC12_B	Comp_E	Timer_A⁽¹⁾	Timer_B⁽²⁾	eUSCI		AES	BSL	I/O	PACKAGE
DEVICE	FRAM (KB)	SRAM (KB)	CLOCK SYSTEM	ADC12_B	Comp_E	Timer_A⁽¹⁾	Timer_B⁽²⁾	A⁽³⁾	B⁽⁴⁾	AES	BSL	I/O	PACKAGE
MSP430FR5969	64	2	DCO HFXT LFXT	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	40	48 RGZ
MSP430FR59691	64	2	DCO HFXT LFXT	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	I²C	40	48 RGZ
MSP430FR5968	48	2	DCO HFXT LFXT	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	40	48 RGZ
MSP430FR5967	32	1	DCO HFXT LFXT	16 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	40	48 RGZ

MSP430FR5949	64	2	DCO LFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	33	40 RHA
MSP430FR5949	64	2	DCO LFXT	12 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	31	38 DA
MSP430FR5948	48	2	DCO LFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	33	40 RHA
MSP430FR5948	48	2	DCO LFXT	12 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	31	38 DA
MSP430FR5947	32	1	DCO LFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	33	40 RHA
MSP430FR5947	32	1	DCO LFXT	12 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	31	38 DA
MSP430FR59471	32	1	DCO LFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	I²C	33	40 RHA

MSP430FR5959	64	2	DCO HFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	33	40 RHA
MSP430FR5959	64	2	DCO HFXT	12 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	31	38 DA
MSP430FR5958	48	2	DCO HFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	33	40 RHA
MSP430FR5958	48	2	DCO HFXT	12 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	31	38 DA
MSP430FR5957	32	1	DCO HFXT	14 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	33	40 RHA
MSP430FR5957	32	1	DCO HFXT	12 ext, 2 int ch.	16 ch.	3, 3⁽⁵⁾ 2, 2⁽⁶⁾	7	2	1	yes	UART	31	38 DA

(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.

(4) eUSCI_B supports I²C with multiple slave addresses, and SPI.

(5) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.

(6) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).

(7) For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.

(8) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.