ZHCSF37C March   2016  – August 2018 MSP430FR5962 , MSP430FR5964 , MSP430FR5992 , MSP430FR5994 , MSP430FR59941

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Packaging Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
        3. Table 5-10 Typical Wake-up Charge
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  LEA (Low-Energy Accelerator) (MSP430FR599x Only)
        1. Table 5-14 Low Energy Accelerator Performance
      7. 5.12.7  Timer_A and Timer_B
        1. Table 5-15 Timer_A
        2. Table 5-16 Timer_B
      8. 5.12.8  eUSCI
        1. Table 5-17 eUSCI (UART Mode) Clock Frequency
        2. Table 5-18 eUSCI (UART Mode)
        3. Table 5-19 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-20 eUSCI (SPI Master Mode)
        5. Table 5-21 eUSCI (SPI Slave Mode)
        6. Table 5-22 eUSCI (I2C Mode)
      9. 5.12.9  ADC12_B
        1. Table 5-23 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-24 12-Bit ADC, Timing Parameters
        3. Table 5-25 12-Bit ADC, Linearity Parameters
        4. Table 5-26 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-27 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-28 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-29 12-Bit ADC, External Reference
      10. 5.12.10 Reference
        1. Table 5-30 REF, Built-In Reference
      11. 5.12.11 Comparator
        1. Table 5-31 Comparator_E
      12. 5.12.12 FRAM
        1. Table 5-32 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-33 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Low-Energy Accelerator (LEA) for Signal Processing (MSP430FR599x Only)
    4. 6.4  Operating Modes
      1. 6.4.1 Peripherals in Low-Power Modes
      2. 6.4.2 Idle Currents of Peripherals in LPM3 and LPM4
    5. 6.5  Interrupt Vector Table and Signatures
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM Controller A (FRCTL_A)
    9. 6.9  RAM
    10. 6.10 Tiny RAM
    11. 6.11 Memory Protection Unit (MPU) Including IP Encapsulation
    12. 6.12 Peripherals
      1. 6.12.1  Digital I/O
      2. 6.12.2  Oscillator and Clock System (CS)
      3. 6.12.3  Power-Management Module (PMM)
      4. 6.12.4  Hardware Multiplier (MPY)
      5. 6.12.5  Real-Time Clock (RTC_C)
      6. 6.12.6  Watchdog Timer (WDT_A)
      7. 6.12.7  System Module (SYS)
      8. 6.12.8  DMA Controller
      9. 6.12.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.12.10 TA0, TA1, and TA4
      11. 6.12.11 TA2 and TA3
      12. 6.12.12 TB0
      13. 6.12.13 ADC12_B
      14. 6.12.14 Comparator_E
      15. 6.12.15 CRC16
      16. 6.12.16 CRC32
      17. 6.12.17 AES256 Accelerator
      18. 6.12.18 True Random Seed
      19. 6.12.19 Shared Reference (REF)
      20. 6.12.20 Embedded Emulation
        1. 6.12.20.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.12.20.2 EnergyTrace++ Technology
    13. 6.13 Input/Output Diagrams
      1. 6.13.1  Capacitive Touch Functionality on Ports P1 to P8, and PJ
      2. 6.13.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.13.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.13.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.13.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.13.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.13.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.13.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.13.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.13.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.13.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.13.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.13.13 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      14. 6.13.14 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      15. 6.13.15 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      16. 6.13.16 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      17. 6.13.17 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      18. 6.13.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 6.13.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      20. 6.13.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    14. 6.14 Device Descriptors (TLV)
    15. 6.15 Memory Map
      1. 6.15.1 Peripheral File Map
    16. 6.16 Identification
      1. 6.16.1 Revision Identification
      2. 6.16.2 Device Identification
      3. 6.16.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1  入门和下一步
    2. 8.2  器件命名规则
    3. 8.3  工具与软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  出口管制提示
    10. 8.10 术语表
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.15.1 Peripheral File Map

Table 6-42 lists the base address and offset range for the supported module registers. For complete module register descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.

Table 6-42 Peripherals

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE
Special Functions (see Table 6-43) 0100h 000h to 01Fh
PMM (see Table 6-44) 0120h 000h to 01Fh
FRAM Controller A (see Table 6-45) 0140h 000h to 00Fh
CRC16 (see Table 6-46) 0150h 000h to 007h
RAM Controller (see Table 6-47) 0158h 000h to 00Fh
Watchdog (see Table 6-48) 015Ch 000h to 001h
CS (see Table 6-49) 0160h 000h to 00Fh
SYS (see Table 6-50) 0180h 000h to 01Fh
Shared Reference (see Table 6-51) 01B0h 000h to 001h
Port P1, P2 (see Table 6-52) 0200h 000h to 01Fh
Port P3, P4 (see Table 6-53) 0220h 000h to 01Fh
Port P5, P6 (see Table 6-54) 0240h 000h to 01Fh
Port P7, P8 (see Table 6-55) 0260h 000h to 01Fh
Port PJ (see Table 6-56) 0320h 000h to 01Fh
TA0 (see Table 6-57) 0340h 000h to 02Fh
TA1 (see Table 6-58) 0380h 000h to 02Fh
TB0 (see Table 6-59) 03C0h 000h to 02Fh
TA2 (see Table 6-60) 0400h 000h to 02Fh
Capacitive Touch I/O 0 (see Table 6-61) 0430h 000h to 00Fh
TA3 (see Table 6-62) 0440h 000h to 02Fh
Capacitive Touch I/O 1 (see Table 6-63) 0470h 000h to 00Fh
Real-Time Clock (RTC_C) (see Table 6-64) 04A0h 000h to 01Fh
32-Bit Hardware Multiplier (see Table 6-65) 04C0h 000h to 02Fh
DMA General Control (see Table 6-66) 0500h 000h to 00Fh
DMA Channel 0 (see Table 6-66) 0510h 000h to 00Fh
DMA Channel 1 (see Table 6-66) 0520h 000h to 00Fh
DMA Channel 2 (see Table 6-66) 0530h 000h to 00Fh
DMA Channel 3 (see Table 6-66) 0540h 000h to 00Fh
DMA Channel 4 (see Table 6-66) 0550h 000h to 00Fh
DMA Channel 5 (see Table 6-66) 0560h 000h to 00Fh
MPU Control (see Table 6-67) 05A0h 000h to 00Fh
eUSCI_A0 (see Table 6-68) 05C0h 000h to 01Fh
eUSCI_A1 (see Table 6-69) 05E0h 000h to 01Fh
eUSCI_A2 (see Table 6-70) 0600h 000h to 01Fh
eUSCI_A3 (see Table 6-71) 0620h 000h to 01Fh
eUSCI_B0 (see Table 6-72) 0640h 000h to 02Fh
eUSCI_B1 (see Table 6-73) 0680h 000h to 02Fh
eUSCI_B2 (see Table 6-74) 06C0h 000h to 02Fh
eUSCI_B3 (see Table 6-75) 0700h 000h to 02Fh
TA4 (see Table 6-76) 07C0h 000h to 02Fh
ADC12_B (see Table 6-77) 0800h 000h to 09Fh
Comparator_E (see Table 6-78) 08C0h 000h to 00Fh
CRC32 (see Table 6-79) 0980h 000h to 02Fh
AES (see Table 6-80) 09C0h 000h to 00Fh
LEA(1) (MSP430FR599x only) 0A80h 000h to 07Fh
(1) Direct access to LEA registers is not supported, and TI recommends using the optimized Digital Signal Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.

Table 6-43 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION ACRONYM OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h

Table 6-44 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION ACRONYM OFFSET
PMM control 0 PMMCTL0 00h
PMM interrupt flags PMMIFG 0Ah
PM5 control 0 PM5CTL0 10h

Table 6-45 FRAM Controller A (FRCTL_A) Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION ACRONYM OFFSET
FRAM control 0 FRCTL0 00h
General control 0 GCCTL0 04h
General control 1 GCCTL1 06h

Table 6-46 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION ACRONYM OFFSET
CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h

Table 6-47 RAM Controller Registers (Base Address: 0158h)

REGISTER DESCRIPTION ACRONYM OFFSET
RAM controller control 0 RCCTL0 00h

Table 6-48 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION ACRONYM OFFSET
Watchdog timer control WDTCTL 00h

Table 6-49 CS Registers (Base Address: 0160h)

REGISTER DESCRIPTION ACRONYM OFFSET
CS control 0 CSCTL0 00h
CS control 1 CSCTL1 02h
CS control 2 CSCTL2 04h
CS control 3 CSCTL3 06h
CS control 4 CSCTL4 08h
CS control 5 CSCTL5 0Ah
CS control 6 CSCTL6 0Ch

Table 6-50 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION ACRONYM OFFSET
System control SYSCTL 00h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh

Table 6-51 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION ACRONYM OFFSET
Shared reference control REFCTL 00h

Table 6-52 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 resistor enable P1REN 06h
Port P1 selection 0 P1SEL0 0Ah
Port P1 selection 1 P1SEL1 0Ch
Port P1 interrupt vector word P1IV 0Eh
Port P1 complement selection P1SELC 16h
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 input P2IN 01h
Port P2 output P2OUT 03h
Port P2 direction P2DIR 05h
Port P2 resistor enable P2REN 07h
Port P2 selection 0 P2SEL0 0Bh
Port P2 selection 1 P2SEL1 0Dh
Port P2 complement selection P2SELC 17h
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh

Table 6-53 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P3 input P3IN 00h
Port P3 output P3OUT 02h
Port P3 direction P3DIR 04h
Port P3 resistor enable P3REN 06h
Port P3 selection 0 P3SEL0 0Ah
Port P3 selection 1 P3SEL1 0Ch
Port P3 interrupt vector word P3IV 0Eh
Port P3 complement selection P3SELC 16h
Port P3 interrupt edge select P3IES 18h
Port P3 interrupt enable P3IE 1Ah
Port P3 interrupt flag P3IFG 1Ch
Port P4 input P4IN 01h
Port P4 output P4OUT 03h
Port P4 direction P4DIR 05h
Port P4 resistor enable P4REN 07h
Port P4 selection 0 P4SEL0 0Bh
Port P4 selection 1 P4SEL1 0Dh
Port P4 complement selection P4SELC 17h
Port P4 interrupt vector word P4IV 1Eh
Port P4 interrupt edge select P4IES 19h
Port P4 interrupt enable P4IE 1Bh
Port P4 interrupt flag P4IFG 1Dh

Table 6-54 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P5 input P5IN 00h
Port P5 output P5OUT 02h
Port P5 direction P5DIR 04h
Port P5 resistor enable P5REN 06h
Port P5 selection 0 P5SEL0 0Ah
Port P5 selection 1 P5SEL1 0Ch
Port P5 interrupt vector word P5IV 0Eh
Port P5 complement selection P5SELC 16h
Port P5 interrupt edge select P5IES 18h
Port P5 interrupt enable P5IE 1Ah
Port P5 interrupt flag P5IFG 1Ch
Port P6 input P6IN 01h
Port P6 output P6OUT 03h
Port P6 direction P6DIR 05h
Port P6 resistor enable P6REN 07h
Port P6 selection 0 P6SEL0 0Bh
Port P6 selection 1 P6SEL1 0Dh
Port P6 complement selection P6SELC 17h
Port P6 interrupt vector word P6IV 1Eh
Port P6 interrupt edge select P6IES 19h
Port P6 interrupt enable P6IE 1Bh
Port P6 interrupt flag P6IFG 1Dh

Table 6-55 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port P7 input P7IN 00h
Port P7 output P7OUT 02h
Port P7 direction P7DIR 04h
Port P7 resistor enable P7REN 06h
Port P7 selection 0 P7SEL0 0Ah
Port P7 selection 1 P7SEL1 0Ch
Port P7 interrupt vector word P7IV 0Eh
Port P7 complement selection P7SELC 16h
Port P7 interrupt edge select P7IES 18h
Port P7 interrupt enable P7IE 1Ah
Port P7 interrupt flag P7IFG 1Ch
Port P8 input P8IN 01h
Port P8 output P8OUT 03h
Port P8 direction P8DIR 05h
Port P8 resistor enable P8REN 07h
Port P8 selection 0 P8SEL0 0Bh
Port P8 selection 1 P8SEL1 0Dh
Port P8 complement selection P8SELC 17h
Port P8 interrupt vector word P8IV 1Eh
Port P8 interrupt edge select P8IES 19h
Port P8 interrupt enable P8IE 1Bh
Port P8 interrupt flag P8IFG 1Dh

Table 6-56 Port PJ Registers (Base Address: 0320h)

REGISTER DESCRIPTION ACRONYM OFFSET
Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ resistor enable PJREN 06h
Port PJ selection 0 PJSEL0 0Ah
Port PJ selection 1 PJSEL1 0Ch
Port PJ complement selection PJSELC 16h

Table 6-57 TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION ACRONYM OFFSET
TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 1 TA0CCTL1 04h
Capture/compare control 2 TA0CCTL2 06h
TA0 counter TA0R 10h
Capture/compare 0 TA0CCR0 12h
Capture/compare 1 TA0CCR1 14h
Capture/compare 2 TA0CCR2 16h
TA0 expansion 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh

Table 6-58 TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION ACRONYM OFFSET
TA1 control TA1CTL 00h
Capture/compare control 0 TA1CCTL0 02h
Capture/compare control 1 TA1CCTL1 04h
Capture/compare control 2 TA1CCTL2 06h
TA1 counter TA1R 10h
Capture/compare 0 TA1CCR0 12h
Capture/compare 1 TA1CCR1 14h
Capture/compare 2 TA1CCR2 16h
TA1 expansion 0 TA1EX0 20h
TA1 interrupt vector TA1IV 2Eh

Table 6-59 TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 1 TB0CCTL1 04h
Capture/compare control 2 TB0CCTL2 06h
Capture/compare control 3 TB0CCTL3 08h
Capture/compare control 4 TB0CCTL4 0Ah
Capture/compare control 5 TB0CCTL5 0Ch
Capture/compare control 6 TB0CCTL6 0Eh
TB0 counter TB0R 10h
Capture/compare 0 TB0CCR0 12h
Capture/compare 1 TB0CCR1 14h
Capture/compare 2 TB0CCR2 16h
Capture/compare 3 TB0CCR3 18h
Capture/compare 4 TB0CCR4 1Ah
Capture/compare 5 TB0CCR5 1Ch
Capture/compare 6 TB0CCR6 1Eh
TB0 expansion 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh

Table 6-60 TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION ACRONYM OFFSET
TA2 control TA2CTL 00h
Capture/compare control 0 TA2CCTL0 02h
Capture/compare control 1 TA2CCTL1 04h
TA2 counter TA2R 10h
Capture/compare 0 TA2CCR0 12h
Capture/compare 1 TA2CCR1 14h
TA2 expansion 0 TA2EX0 20h
TA2 interrupt vector TA2IV 2Eh

Table 6-61 Capacitive Touch I/O 0 Registers (Base Address: 0430h)

REGISTER DESCRIPTION ACRONYM OFFSET
Capacitive Touch I/O 0 control CAPTIO0CTL 0Eh

Table 6-62 TA3 Registers (Base Address: 0440h)

REGISTER DESCRIPTION ACRONYM OFFSET
TA3 control TA3CTL 00h
Capture/compare control 0 TA3CCTL0 02h
Capture/compare control 1 TA3CCTL1 04h
TA3 counter TA3R 10h
Capture/compare 0 TA3CCR0 12h
Capture/compare 1 TA3CCR1 14h
TA3 expansion 0 TA3EX0 20h
TA3 interrupt vector TA3IV 2Eh

Table 6-63 Capacitive Touch I/O 1 Registers (Base Address: 0470h)

REGISTER DESCRIPTION ACRONYM OFFSET
Capacitive Touch I/O 1 control CAPTIO1CTL 0Eh

Table 6-64 RTC_C Registers (Base Address: 04A0h)

REGISTER DESCRIPTION ACRONYM OFFSET
RTC control 0 RTCCTL0 00h
RTC password RTCPWD 01h
RTC control 1 RTCCTL1 02h
RTC control 3 RTCCTL3 03h
RTC offset calibration RTCOCAL 04h
RTC temperature compensation RTCTCMP 06h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds/counter 1 RTCSEC/RTCNT1 10h
RTC minutes/counter 2 RTCMIN/RTCNT2 11h
RTC hours/counter 3 RTCHOUR/RTCNT3 12h
RTC day of week/counter 4 RTCDOW/RTCNT4 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year RTCYEAR 16h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh
Binary-to-BCD conversion BIN2BCD 1Ch
BCD-to-binary conversion BCD2BIN 1Eh

Table 6-65 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control 0 MPY32CTL0 2Ch

Table 6-66 DMA Registers (Base Address DMA General Control: 0500h,
Channel 0: 0510h, Channel 1: 0520h, Channel 2: 0530h,
Channel 3: 0540h, Channel 4: 0550h, Channel 5: 0560h)

REGISTER DESCRIPTION ACRONYM OFFSET
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah
DMA channel 1 control DMA1CTL 00h
DMA channel 1 source address low DMA1SAL 02h
DMA channel 1 source address high DMA1SAH 04h
DMA channel 1 destination address low DMA1DAL 06h
DMA channel 1 destination address high DMA1DAH 08h
DMA channel 1 transfer size DMA1SZ 0Ah
DMA channel 2 control DMA2CTL 00h
DMA channel 2 source address low DMA2SAL 02h
DMA channel 2 source address high DMA2SAH 04h
DMA channel 2 destination address low DMA2DAL 06h
DMA channel 2 destination address high DMA2DAH 08h
DMA channel 2 transfer size DMA2SZ 0Ah
DMA channel 3 control DMA3CTL 00h
DMA channel 3 source address low DMA3SAL 02h
DMA channel 3 source address high DMA3SAH 04h
DMA channel 3 destination address low DMA3DAL 06h
DMA channel 3 destination address high DMA3DAH 08h
DMA channel 3 transfer size DMA3SZ 0Ah
DMA channel 4 control DMA4CTL 00h
DMA channel 4 source address low DMA4SAL 02h
DMA channel 4 source address high DMA4SAH 04h
DMA channel 4 destination address low DMA4DAL 06h
DMA channel 4 destination address high DMA4DAH 08h
DMA channel 4 transfer size DMA4SZ 0Ah
DMA channel 5 control DMA5CTL 00h
DMA channel 5 source address low DMA5SAL 02h
DMA channel 5 source address high DMA5SAH 04h
DMA channel 5 destination address low DMA5DAL 06h
DMA channel 5 destination address high DMA5DAH 08h
DMA channel 5 transfer size DMA5SZ 0Ah
DMA module control 0 DMACTL0 00h
DMA module control 1 DMACTL1 02h
DMA module control 2 DMACTL2 04h
DMA module control 3 DMACTL3 06h
DMA module control 4 DMACTL4 08h
DMA interrupt vector DMAIV 0Eh

Table 6-67 MPU Control Registers (Base Address: 05A0h)

REGISTER DESCRIPTION ACRONYM OFFSET
MPU control 0 MPUCTL0 00h
MPU control 1 MPUCTL1 02h
MPU segmentation border 2 MPUSEGB2 04h
MPU segmentation border 1 MPUSEGB1 06h
MPU access management MPUSAM 08h
MPU IP control 0 MPUIPC0 0Ah
MPU IP encapsulation segment border 2 MPUIPSEGB2 0Ch
MPU IP encapsulation segment border 1 MPUIPSEGB1 0Eh

Table 6-68 eUSCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_A control word 0 UCA0CTLW0 00h
eUSCI _A control word 1 UCA0CTLW1 02h
eUSCI_A baud rate 0 UCA0BR0 06h
eUSCI_A baud rate 1 UCA0BR1 07h
eUSCI_A modulation control UCA0MCTLW 08h
eUSCI_A status word UCA0STATW 0Ah
eUSCI_A receive buffer UCA0RXBUF 0Ch
eUSCI_A transmit buffer UCA0TXBUF 0Eh
eUSCI_A LIN control UCA0ABCTL 10h
eUSCI_A IrDA transmit control UCA0IRTCTL 12h
eUSCI_A IrDA receive control UCA0IRRCTL 13h
eUSCI_A interrupt enable UCA0IE 1Ah
eUSCI_A interrupt flags UCA0IFG 1Ch
eUSCI_A interrupt vector word UCA0IV 1Eh

Table 6-69 eUSCI_A1 Registers (Base Address:05E0h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_A control word 0 UCA1CTLW0 00h
eUSCI _A control word 1 UCA1CTLW1 02h
eUSCI_A baud rate 0 UCA1BR0 06h
eUSCI_A baud rate 1 UCA1BR1 07h
eUSCI_A modulation control UCA1MCTLW 08h
eUSCI_A status word UCA1STATW 0Ah
eUSCI_A receive buffer UCA1RXBUF 0Ch
eUSCI_A transmit buffer UCA1TXBUF 0Eh
eUSCI_A LIN control UCA1ABCTL 10h
eUSCI_A IrDA transmit control UCA1IRTCTL 12h
eUSCI_A IrDA receive control UCA1IRRCTL 13h
eUSCI_A interrupt enable UCA1IE 1Ah
eUSCI_A interrupt flags UCA1IFG 1Ch
eUSCI_A interrupt vector word UCA1IV 1Eh

Table 6-70 eUSCI_A2 Registers (Base Address:0600h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_A control word 0 UCA2CTLW0 00h
eUSCI _A control word 1 UCA2CTLW1 02h
eUSCI_A baud rate 0 UCA2BR0 06h
eUSCI_A baud rate 1 UCA2BR1 07h
eUSCI_A modulation control UCA2MCTLW 08h
eUSCI_A status word UCA2STATW 0Ah
eUSCI_A receive buffer UCA2RXBUF 0Ch
eUSCI_A transmit buffer UCA2TXBUF 0Eh
eUSCI_A LIN control UCA2ABCTL 10h
eUSCI_A IrDA transmit control UCA2IRTCTL 12h
eUSCI_A IrDA receive control UCA2IRRCTL 13h
eUSCI_A interrupt enable UCA2IE 1Ah
eUSCI_A interrupt flags UCA2IFG 1Ch
eUSCI_A interrupt vector word UCA2IV 1Eh

Table 6-71 eUSCI_A3 Registers (Base Address:0620h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_A control word 0 UCA3CTLW0 00h
eUSCI _A control word 1 UCA3CTLW1 02h
eUSCI_A baud rate 0 UCA3BR0 06h
eUSCI_A baud rate 1 UCA3BR1 07h
eUSCI_A modulation control UCA3MCTLW 08h
eUSCI_A status word UCA3STATW 0Ah
eUSCI_A receive buffer UCA3RXBUF 0Ch
eUSCI_A transmit buffer UCA3TXBUF 0Eh
eUSCI_A LIN control UCA3ABCTL 10h
eUSCI_A IrDA transmit control UCA3IRTCTL 12h
eUSCI_A IrDA receive control UCA3IRRCTL 13h
eUSCI_A interrupt enable UCA3IE 1Ah
eUSCI_A interrupt flags UCA3IFG 1Ch
eUSCI_A interrupt vector word UCA3IV 1Eh

Table 6-72 eUSCI_B0 Registers (Base Address: 0640h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_B control word 0 UCB0CTLW0 00h
eUSCI_B control word 1 UCB0CTLW1 02h
eUSCI_B bit rate 0 UCB0BR0 06h
eUSCI_B bit rate 1 UCB0BR1 07h
eUSCI_B status word UCB0STATW 08h
eUSCI_B byte counter threshold UCB0TBCNT 0Ah
eUSCI_B receive buffer UCB0RXBUF 0Ch
eUSCI_B transmit buffer UCB0TXBUF 0Eh
eUSCI_B I2C own address 0 UCB0I2COA0 14h
eUSCI_B I2C own address 1 UCB0I2COA1 16h
eUSCI_B I2C own address 2 UCB0I2COA2 18h
eUSCI_B I2C own address 3 UCB0I2COA3 1Ah
eUSCI_B received address UCB0ADDRX 1Ch
eUSCI_B address mask UCB0ADDMASK 1Eh
eUSCI I2C slave address UCB0I2CSA 20h
eUSCI interrupt enable UCB0IE 2Ah
eUSCI interrupt flags UCB0IFG 2Ch
eUSCI interrupt vector word UCB0IV 2Eh

Table 6-73 eUSCI_B1 Registers (Base Address: 0680h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_B control word 0 UCB1CTLW0 00h
eUSCI_B control word 1 UCB1CTLW1 02h
eUSCI_B bit rate 0 UCB1BR0 06h
eUSCI_B bit rate 1 UCB1BR1 07h
eUSCI_B status word UCB1STATW 08h
eUSCI_B byte counter threshold UCB1TBCNT 0Ah
eUSCI_B receive buffer UCB1RXBUF 0Ch
eUSCI_B transmit buffer UCB1TXBUF 0Eh
eUSCI_B I2C own address 0 UCB1I2COA0 14h
eUSCI_B I2C own address 1 UCB1I2COA1 16h
eUSCI_B I2C own address 2 UCB1I2COA2 18h
eUSCI_B I2C own address 3 UCB1I2COA3 1Ah
eUSCI_B received address UCB1ADDRX 1Ch
eUSCI_B address mask UCB1ADDMASK 1Eh
eUSCI I2C slave address UCB1I2CSA 20h
eUSCI interrupt enable UCB1IE 2Ah
eUSCI interrupt flags UCB1IFG 2Ch
eUSCI interrupt vector word UCB1IV 2Eh

Table 6-74 eUSCI_B2 Registers (Base Address: 06C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_B control word 0 UCB2CTLW0 00h
eUSCI_B control word 1 UCB2CTLW1 02h
eUSCI_B bit rate 0 UCB2BR0 06h
eUSCI_B bit rate 1 UCB2BR1 07h
eUSCI_B status word UCB2STATW 08h
eUSCI_B byte counter threshold UCB2TBCNT 0Ah
eUSCI_B receive buffer UCB2RXBUF 0Ch
eUSCI_B transmit buffer UCB2TXBUF 0Eh
eUSCI_B I2C own address 0 UCB2I2COA0 14h
eUSCI_B I2C own address 1 UCB2I2COA1 16h
eUSCI_B I2C own address 2 UCB2I2COA2 18h
eUSCI_B I2C own address 3 UCB2I2COA3 1Ah
eUSCI_B received address UCB2ADDRX 1Ch
eUSCI_B address mask UCB2ADDMASK 1Eh
eUSCI I2C slave address UCB2I2CSA 20h
eUSCI interrupt enable UCB2IE 2Ah
eUSCI interrupt flags UCB2IFG 2Ch
eUSCI interrupt vector word UCB2IV 2Eh

Table 6-75 eUSCI_B3 Registers (Base Address: 0700h)

REGISTER DESCRIPTION ACRONYM OFFSET
eUSCI_B control word 0 UCB3CTLW0 00h
eUSCI_B control word 1 UCB3CTLW1 02h
eUSCI_B bit rate 0 UCB3BR0 06h
eUSCI_B bit rate 1 UCB3BR1 07h
eUSCI_B status word UCB3STATW 08h
eUSCI_B byte counter threshold UCB3TBCNT 0Ah
eUSCI_B receive buffer UCB3RXBUF 0Ch
eUSCI_B transmit buffer UCB3TXBUF 0Eh
eUSCI_B I2C own address 0 UCB3I2COA0 14h
eUSCI_B I2C own address 1 UCB3I2COA1 16h
eUSCI_B I2C own address 2 UCB3I2COA2 18h
eUSCI_B I2C own address 3 UCB3I2COA3 1Ah
eUSCI_B received address UCB3ADDRX 1Ch
eUSCI_B address mask UCB3ADDMASK 1Eh
eUSCI I2C slave address UCB3I2CSA 20h
eUSCI interrupt enable UCB3IE 2Ah
eUSCI interrupt flags UCB3IFG 2Ch
eUSCI interrupt vector word UCB3IV 2Eh

Table 6-76 TA4 Registers (Base Address: 07C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
TA4 control TA4CTL 00h
Capture/compare control 0 TA4CCTL0 02h
Capture/compare control 1 TA4CCTL1 04h
TA4 counter TA4R 10h
Capture/compare 0 TA4CCR0 12h
Capture/compare 1 TA4CCR1 14h
TA4 expansion 0 TA4EX0 20h
TA4 interrupt vector TA4IV 2Eh

Table 6-77 ADC12_B Registers (Base Address: 0800h)

REGISTER DESCRIPTION ACRONYM OFFSET
ADC12_B control 0 ADC12CTL0 00h
ADC12_B control 1 ADC12CTL1 02h
ADC12_B control 2 ADC12CTL2 04h
ADC12_B control 3 ADC12CTL3 06h
ADC12_B window comparator low threshold register ADC12LO 08h
ADC12_B window comparator high threshold register ADC12HI 0Ah
ADC12_B interrupt flag register 0 ADC12IFGR0 0Ch
ADC12_B interrupt flag register 1 ADC12IFGR1 0Eh
ADC12_B interrupt flag register 2 ADC12IFGR2 10h
ADC12_B interrupt enable register 0 ADC12IER0 12h
ADC12_B interrupt enable register 1 ADC12IER1 14h
ADC12_B interrupt enable register 2 ADC12IER2 16h
ADC12_B interrupt vector ADC12IV 18h
ADC12_B memory control 0 ADC12MCTL0 20h
ADC12_B memory control 1 ADC12MCTL1 22h
ADC12_B memory control 2 ADC12MCTL2 24h
ADC12_B memory control 3 ADC12MCTL3 26h
ADC12_B memory control 4 ADC12MCTL4 28h
ADC12_B memory control 5 ADC12MCTL5 2Ah
ADC12_B memory control 6 ADC12MCTL6 2Ch
ADC12_B memory control 7 ADC12MCTL7 2Eh
ADC12_B memory control 8 ADC12MCTL8 30h
ADC12_B memory control 9 ADC12MCTL9 32h
ADC12_B memory control 10 ADC12MCTL10 34h
ADC12_B memory control 11 ADC12MCTL11 36h
ADC12_B memory control 12 ADC12MCTL12 38h
ADC12_B memory control 13 ADC12MCTL13 3Ah
ADC12_B memory control 14 ADC12MCTL14 3Ch
ADC12_B memory control 15 ADC12MCTL15 3Eh
ADC12_B memory control 16 ADC12MCTL16 40h
ADC12_B memory control 17 ADC12MCTL17 42h
ADC12_B memory control 18 ADC12MCTL18 44h
ADC12_B memory control 19 ADC12MCTL19 46h
ADC12_B memory control 20 ADC12MCTL20 48h
ADC12_B memory control 21 ADC12MCTL21 4Ah
ADC12_B memory control 22 ADC12MCTL22 4Ch
ADC12_B memory control 23 ADC12MCTL23 4Eh
ADC12_B memory control 24 ADC12MCTL24 50h
ADC12_B memory control 25 ADC12MCTL25 52h
ADC12_B memory control 26 ADC12MCTL26 54h
ADC12_B memory control 27 ADC12MCTL27 56h
ADC12_B memory control 28 ADC12MCTL28 58h
ADC12_B memory control 29 ADC12MCTL29 5Ah
ADC12_B memory control 30 ADC12MCTL30 5Ch
ADC12_B memory control 31 ADC12MCTL31 5Eh
ADC12_B memory 0 ADC12MEM0 60h
ADC12_B memory 1 ADC12MEM1 62h
ADC12_B memory 2 ADC12MEM2 64h
ADC12_B memory 3 ADC12MEM3 66h
ADC12_B memory 4 ADC12MEM4 68h
ADC12_B memory 5 ADC12MEM5 6Ah
ADC12_B memory 6 ADC12MEM6 6Ch
ADC12_B memory 7 ADC12MEM7 6Eh
ADC12_B memory 8 ADC12MEM8 70h
ADC12_B memory 9 ADC12MEM9 72h
ADC12_B memory 10 ADC12MEM10 74h
ADC12_B memory 11 ADC12MEM11 76h
ADC12_B memory 12 ADC12MEM12 78h
ADC12_B memory 13 ADC12MEM13 7Ah
ADC12_B memory 14 ADC12MEM14 7Ch
ADC12_B memory 15 ADC12MEM15 7Eh
ADC12_B memory 16 ADC12MEM16 80h
ADC12_B memory 17 ADC12MEM17 82h
ADC12_B memory 18 ADC12MEM18 84h
ADC12_B memory 19 ADC12MEM19 86h
ADC12_B memory 20 ADC12MEM20 88h
ADC12_B memory 21 ADC12MEM21 8Ah
ADC12_B memory 22 ADC12MEM22 8Ch
ADC12_B memory 23 ADC12MEM23 8Eh
ADC12_B memory 24 ADC12MEM24 90h
ADC12_B memory 25 ADC12MEM25 92h
ADC12_B memory 26 ADC12MEM26 94h
ADC12_B memory 27 ADC12MEM27 96h
ADC12_B memory 28 ADC12MEM28 98h
ADC12_B memory 29 ADC12MEM29 9Ah
ADC12_B memory 30 ADC12MEM30 9Ch
ADC12_B memory 31 ADC12MEM31 9Eh

Table 6-78 Comparator_E Registers (Base Address: 08C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
Comparator_E control 0 CECTL0 00h
Comparator_E control 1 CECTL1 02h
Comparator_E control 2 CECTL2 04h
Comparator_E control 3 CECTL3 06h
Comparator_E interrupt CEINT 0Ch
Comparator_E interrupt vector word CEIV 0Eh

Table 6-79 CRC32 Registers (Base Address: 0980h)

REGISTER DESCRIPTION ACRONYM OFFSET
CRC32 data input CRC32DIW0 00h
Reserved 02h
Reserved 04h
CRC32 data input reverse CRC32DIRBW0 06h
CRC32 initialization and result word 0 CRC32INIRESW0 08h
CRC32 initialization and result word 1 CRC32INIRESW1 0Ah
CRC32 result reverse word 1 CRC32RESRW1 0Ch
CRC32 result reverse word 0 CRC32RESRW1 0Eh
CRC16 data input CRC16DIW0 10h
Reserved 12h
Reserved 14h
CRC16 data input reverse CRC16DIRBW0 16h
CRC16 initialization and result word 0 CRC16INIRESW0 18h
Reserved 1Ah
Reserved 1Ch
CRC16 result reverse word 0 CRC16RESRW0 1Eh
Reserved 20h
Reserved 22h
Reserved 24h
Reserved 26h
Reserved 28h
Reserved 2Ah
Reserved 2Ch
Reserved 2Eh

Table 6-80 AES Accelerator Registers (Base Address: 09C0h)

REGISTER DESCRIPTION ACRONYM OFFSET
AES accelerator control 0 AESACTL0 00h
Reserved 02h
AES accelerator status AESASTAT 04h
AES accelerator key AESAKEY 06h
AES accelerator data in AESADIN 008h
AES accelerator data out AESADOUT 00Ah
AES accelerator XORed data in AESAXDIN 00Ch
AES accelerator XORed data in (no trigger) AESAXIN 00Eh
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