ZHCSJA6B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431
PRODUCTION DATA
The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password. Table 9-6 lists the pins that are required for use of the BSL. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see the MSP430™ FRAM Devices Bootloader (BSL) User's Guide. More information on the BSL can be found at www.ti.com/tool/mspbsl.
DEVICE SIGNAL | BSL FUNCTION |
---|---|
RST/NMI/SBWTDIO | Entry sequence signal |
TEST/SBWTCK | Entry sequence signal |
P2.0 | Devices with UART BSL (FRxxxx): Data transmit |
P2.1 | Devices with UART BSL (FRxxxx): Data receive |
P1.6 | Devices with I2C BSL (FRxxxx1): Data |
P1.7 | Devices with I2C BSL (FRxxxx1): Clock |
DVCC, AVCC | Power supply |
DVSS, AVSS | Ground supply |