ZHCSCV0C August   2014  – August 2018 MSP430FR6877 , MSP430FR6879 , MSP430FR68791

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions – MSP430FR687x and MSP430FR687x1
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1 Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2 Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3 Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4 Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5 Peripherals
        1. 5.13.5.1 Digital I/Os
          1. Table 5-11 Digital Inputs
          2. Table 5-12 Digital Outputs
          3. 5.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
          4. Table 5-13 Pin-Oscillator Frequency, Ports Px
          5. 5.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
        2. 5.13.5.2 Timer_A and Timer_B
          1. Table 5-14 Timer_A
          2. Table 5-15 Timer_B
        3. 5.13.5.3 eUSCI
          1. Table 5-16 eUSCI (UART Mode) Clock Frequency
          2. Table 5-17 eUSCI (UART Mode)
          3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
          4. Table 5-19 eUSCI (SPI Master Mode)
          5. Table 5-20 eUSCI (SPI Slave Mode)
          6. Table 5-21 eUSCI (I2C Mode)
        4. 5.13.5.4 LCD Controller
          1. Table 5-22 LCD_C, Recommended Operating Conditions
          2. Table 5-23 LCD_C Electrical Characteristics
        5. 5.13.5.5 ADC
          1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
          2. Table 5-25 12-Bit ADC, Timing Parameters
          3. Table 5-26 12-Bit ADC, Linearity Parameters With External Reference
          4. Table 5-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
          5. Table 5-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
          6. Table 5-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
          7. Table 5-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
          8. Table 5-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
          9. Table 5-32 12-Bit ADC, Temperature Sensor and Built-In V1/2
          10. Table 5-33 12-Bit ADC, External Reference
        6. 5.13.5.6 Reference
          1. Table 5-34 REF, Built-In Reference
        7. 5.13.5.7 Comparator
          1. Table 5-35 Comparator_E
        8. 5.13.5.8 FRAM Controller
          1. Table 5-36 FRAM
      6. 5.13.6 Emulation and Debug
        1. Table 5-37 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier (MPY)
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 True Random Seed
      19. 6.11.19 Shared Reference (REF_A)
      20. 6.11.20 LCD_C
      21. 6.11.21 Embedded Emulation
        1. 6.11.21.1 Embedded Emulation Module (EEM)
        2. 6.11.21.2 EnergyTrace++™ Technology
      22. 6.11.22 Input/Output Diagrams
        1. 6.11.22.1  Digital I/O Functionality – Ports P1 to P10
        2. 6.11.22.2  Capacitive Touch Functionality Ports P1 to P10 and PJ
        3. 6.11.22.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.22.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.22.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.22.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
        7. 6.11.22.7  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        8. 6.11.22.8  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
        9. 6.11.22.9  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
        10. 6.11.22.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        11. 6.11.22.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
        12. 6.11.22.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
        13. 6.11.22.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
        14. 6.11.22.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
        15. 6.11.22.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
        16. 6.11.22.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        17. 6.11.22.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
        18. 6.11.22.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        19. 6.11.22.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        20. 6.11.22.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1  入门和后续步骤
    2. 8.2  器件命名规则
    3. 8.3  工具和软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  出口管制提示
    10. 8.10 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.1 特性

  • 嵌入式微控制器
    • 高达 16MHz 时钟频率的 16 位 RISC 架构
    • 3.6V 至 1.8V 的宽电源电压范围（最低电源电压受限于 SVS 电平，请参阅 SVS 规格）
  • 经优化的超低功耗模式
    • 工作模式：大约 100µA/MHz
    • 待机（具有低功率低频内部时钟源 (VLO) 的 LPM3）：0.4µA（典型值）
    • 实时时钟 (RTC) (LPM3.5)：0.35µA（典型值） (1)
    • 关断 (LPM4.5)：0.02µA（典型值）
      • 1. 实时时钟 (RTC) 由 3.7pF 晶振计时。
  • 超低功耗铁电 RAM (FRAM)
    • 高达 128KB 的非易失性存储器
    • 超低功耗写入
    • 125ns 每个字的快速写入（4ms 内写入 64KB）
    • 统一标准存储器 = 单个空间内的程序 + 数据 + 存储
    • 1015 写入周期持久性
    • 抗辐射和非磁性
  • 智能数字外设
    • 32 位硬件乘法器 (MPY)
    • 三通道内部直接存储器存取 (DMA)
    • 带有日历和和报警功能的 RTC
    • 5 个 16 位计时器，每个计时器具有多达 7 个捕捉/比较寄存器
    • 16 位和 32 位循环冗余校验器（CRC16、CRC32）
  • 高性能模拟
    • 16 通道模拟比较器
    • 12 位模数转换器 (ADC)，具有内部基准和采样保持以及多达 16 个外部输入通道
    • 具有高达 320 段对比度控制的集成 LCD 驱动器
  • 多功能输入/输出端口
    • 所有 P1 至 P10 以及 PJ 引脚均支持电容式触控功能，无需外部组件
    • 可每位、每字节和每字访问（成对访问）
    • 可通过 P1、P2、P3 和 P4 端口从 LPM 唤醒，边沿可选
    • 所有端口上可编程上拉和下拉
  • 代码安全性
    • 针对随机数生成算法的真随机种子
  • 增强型串行通信
    • eUSCI_A0 和 eUSCI_A1 支持：
      • 支持自动波特率侦测的通用异步收发器 (UART)
      • IrDA 编码和解码
      • SPI
    • eUSCI_B0 和 eUSCI_B1 均支持：
      • 支持多从设备寻址的 I2C
      • SPI
    • 硬件 UART 和 I2C 引导加载程序 (BSL)
  • 灵活时钟系统
    • 具有 10 个可选厂家调整频率的定频数控振荡器 (DCO)
    • 低功率低频内部时钟源 (VLO)
    • 32kHz 晶振 (LFXT)
    • 高频晶振 (HFXT)
  • 开发工具和软件
    • 自由的专业开发环境 具有 EnergyTrace++™技术
    • 实验和开发套件
  • 系列米6体育平台手机版_好二三四成员
  • 要获得完整的模块说明，请参见《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》
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