ZHCSCV0C
August 2014 – August 2018
MSP430FR6877
,
MSP430FR6879
,
MSP430FR68791
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
功能方框图
2
修订历史记录
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagrams
4.2
Signal Descriptions
Table 4-1
Signal Descriptions – MSP430FR687x and MSP430FR687x1
4.3
Pin Multiplexing
4.4
Connection of Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Typical Characteristics, Active Mode Supply Currents
5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
5.7
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
5.8
Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
5.9
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
5.10
Typical Characteristics, Low-Power Mode Supply Currents
5.11
Typical Characteristics, Current Consumption per Module
5.12
Thermal Resistance Characteristics
5.13
Timing and Switching Characteristics
5.13.1
Power Supply Sequencing
Table 5-1
Brownout and Device Reset Power Ramp Requirements
Table 5-2
SVS
5.13.2
Reset Timing
Table 5-3
Reset Input
5.13.3
Clock Specifications
Table 5-4
Low-Frequency Crystal Oscillator, LFXT
Table 5-5
High-Frequency Crystal Oscillator, HFXT
Table 5-6
DCO
Table 5-7
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Table 5-8
Module Oscillator (MODOSC)
5.13.4
Wake-up Characteristics
Table 5-9
Wake-up Times From Low-Power Modes and Reset
Table 5-10
Typical Wake-up Charge
5.13.4.1
Typical Characteristics, Average LPM Currents vs Wake-up Frequency
5.13.5
Peripherals
5.13.5.1
Digital I/Os
Table 5-11
Digital Inputs
Table 5-12
Digital Outputs
5.13.5.1.1
Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
Table 5-13
Pin-Oscillator Frequency, Ports Px
5.13.5.1.2
Typical Characteristics, Pin-Oscillator Frequency
5.13.5.2
Timer_A and Timer_B
Table 5-14
Timer_A
Table 5-15
Timer_B
5.13.5.3
eUSCI
Table 5-16
eUSCI (UART Mode) Clock Frequency
Table 5-17
eUSCI (UART Mode)
Table 5-18
eUSCI (SPI Master Mode) Clock Frequency
Table 5-19
eUSCI (SPI Master Mode)
Table 5-20
eUSCI (SPI Slave Mode)
Table 5-21
eUSCI (I2C Mode)
5.13.5.4
LCD Controller
Table 5-22
LCD_C, Recommended Operating Conditions
Table 5-23
LCD_C Electrical Characteristics
5.13.5.5
ADC
Table 5-24
12-Bit ADC, Power Supply and Input Range Conditions
Table 5-25
12-Bit ADC, Timing Parameters
Table 5-26
12-Bit ADC, Linearity Parameters With External Reference
Table 5-27
12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
Table 5-28
12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
Table 5-29
12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
Table 5-30
12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
Table 5-31
12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
Table 5-32
12-Bit ADC, Temperature Sensor and Built-In V1/2
Table 5-33
12-Bit ADC, External Reference
5.13.5.6
Reference
Table 5-34
REF, Built-In Reference
5.13.5.7
Comparator
Table 5-35
Comparator_E
5.13.5.8
FRAM Controller
Table 5-36
FRAM
5.13.6
Emulation and Debug
Table 5-37
JTAG and Spy-Bi-Wire Interface
6
Detailed Description
6.1
Overview
6.2
CPU
6.3
Operating Modes
6.3.1
Peripherals in Low-Power Modes
6.3.1.1
Idle Currents of Peripherals in LPM3 and LPM4
6.4
Interrupt Vector Table and Signatures
6.5
Bootloader (BSL)
6.6
JTAG Operation
6.6.1
JTAG Standard Interface
6.6.2
Spy-Bi-Wire Interface
6.7
FRAM
6.8
RAM
6.9
Tiny RAM
6.10
Memory Protection Unit Including IP Encapsulation
6.11
Peripherals
6.11.1
Digital I/O
6.11.2
Oscillator and Clock System (CS)
6.11.3
Power-Management Module (PMM)
6.11.4
Hardware Multiplier (MPY)
6.11.5
Real-Time Clock (RTC_C)
6.11.6
Watchdog Timer (WDT_A)
6.11.7
System Module (SYS)
6.11.8
DMA Controller
6.11.9
Enhanced Universal Serial Communication Interface (eUSCI)
6.11.10
Timer_A TA0, Timer_A TA1
6.11.11
Timer_A TA2
6.11.12
Timer_A TA3
6.11.13
Timer_B TB0
6.11.14
ADC12_B
6.11.15
Comparator_E
6.11.16
CRC16
6.11.17
CRC32
6.11.18
True Random Seed
6.11.19
Shared Reference (REF_A)
6.11.20
LCD_C
6.11.21
Embedded Emulation
6.11.21.1
Embedded Emulation Module (EEM)
6.11.21.2
EnergyTrace++™ Technology
6.11.22
Input/Output Diagrams
6.11.22.1
Digital I/O Functionality – Ports P1 to P10
6.11.22.2
Capacitive Touch Functionality Ports P1 to P10 and PJ
6.11.22.3
Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
6.11.22.4
Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
6.11.22.5
Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
6.11.22.6
Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
6.11.22.7
Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
6.11.22.8
Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
6.11.22.9
Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
6.11.22.10
Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
6.11.22.11
Port P6 (P6.7) Input/Output With Schmitt Trigger
6.11.22.12
Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
6.11.22.13
Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
6.11.22.14
Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
6.11.22.15
Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
6.11.22.16
Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
6.11.22.17
Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
6.11.22.18
Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
6.11.22.19
Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
6.11.22.20
Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
6.12
Device Descriptors (TLV)
6.13
Memory
6.13.1
Peripheral File Map
6.14
Identification
6.14.1
Revision Identification
6.14.2
Device Identification
6.14.3
JTAG Identification
7
Applications, Implementation, and Layout
7.1
Device Connection and Layout Fundamentals
7.1.1
Power Supply Decoupling and Bulk Capacitors
7.1.2
External Oscillator
7.1.3
JTAG
7.1.4
Reset
7.1.5
Unused Pins
7.1.6
General Layout Recommendations
7.1.7
Do's and Don'ts
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC12_B Peripheral
7.2.1.1
Partial Schematic
7.2.1.2
Design Requirements
7.2.1.3
Detailed Design Procedure
7.2.1.4
Layout Guidelines
7.2.2
LCD_C Peripheral
7.2.2.1
Partial Schematic
7.2.2.2
Design Requirements
7.2.2.3
Detailed Design Procedure
7.2.2.4
Layout Guidelines
8
器件和文档支持
8.1
入门和后续步骤
8.2
器件命名规则
8.3
工具和软件
8.4
文档支持
8.5
相关链接
8.6
社区资源
8.7
商标
8.8
静电放电警告
8.9
出口管制提示
8.10
Glossary
9
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
PN|80
MTQF010B
PZ|100
MTQF013A
散热焊盘机械数据 (封装 | 引脚)
PZ|100
QFND428
订购信息
zhcscv0c_oa
zhcscv0c_pm
Table 5-3
Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V
CC
MIN
MAX
UNIT
t
(RST)
External reset pulse duration on
RST
(1)
2.2 V, 3.0 V
2
µs
(1)
Not applicable if the
RST
/NMI pin is configured as NMI
.
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