米6体育平台手机版

ZHCSI49C September 2014 – March 2021

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PW|28
- MPDS364
RHB|32
- MPQF130D

散热焊盘机械数据 (封装 | 引脚)

RHB|32
- QFND257K

订购信息

8.7.8.4 eUSCI (SPI Master Mode) Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock	UCSTEM = 1, UCMODEx = 01 or 10	2.2 V, 3 V	150		ns
t_STE,LAG	STE lag time, Last clock to STE inactive	UCSTEM = 1, UCMODEx = 01 or 10	2.2 V, 3 V	200		ns
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 0, UCMODEx = 01 or 10	2.2 V		40	ns
t_STE,ACC	STE access time, STE active to SIMO data out	UCSTEM = 0, UCMODEx = 01 or 10	3 V		30	ns
t_STE,DIS	STE disable time, STE inactive to SIMO high impedance	UCSTEM = 0, UCMODEx = 01 or 10	2.2 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SIMO high impedance	UCSTEM = 0, UCMODEx = 01 or 10	3 V		30	ns
t_SU,MI	SOMI input data setup time		2.2 V	50		ns
t_SU,MI	SOMI input data setup time		3 V	30		ns
t_HD,MI	SOMI input data hold time		2.2 V, 3 V	0		ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2.2 V		7	ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3 V		5	ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	2.2 V, 3 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)})
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, refer to the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 8-10 and Figure 8-11.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in Figure 8-10 and Figure 8-11.

Figure 8-10 SPI Master Mode, CKPH = 0

Figure 8-11 SPI Master Mode, CKPH = 1