米6体育平台手机版

ZHCSI49C September 2014 – March 2021

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PW|28
- MPDS364
RHB|32
- MPQF130D

散热焊盘机械数据 (封装 | 引脚)

RHB|32
- QFND257K

订购信息

8.7.8.5 eUSCI (SPI Slave Mode) Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock		2.2 V, 3 V	3		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		2.2 V, 3 V	0		ns
t_STE,ACC	STE access time, STE active to SOMI data out		2.2 V		35	ns
t_STE,ACC	STE access time, STE active to SOMI data out		3 V		25	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		2.2 V, 3 V		35	ns
t_SU,SI	SIMO input data setup time		2.2 V, 3 V	1		ns
t_HD,SI	SIMO input data hold time		2.2 V, 3 V	5		ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2.2 V		35	ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3 V		25	ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	2.2 V	35		ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	3 V	25		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)})
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, refer to the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 8-12 and Figure 8-13.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in Figure 8-12 and Figure 8-13.

Figure 8-12 SPI Slave Mode, CKPH = 0

Figure 8-13 SPI Slave Mode, CKPH = 1