ZHCSI49C September   2014  – March 2021

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Active Mode Supply Current (Into VCC) Excluding External Current
    5. 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6 Thermal Resistance Characteristics
    7. 8.7 Timing and Switching Characteristics
      1. 8.7.1  Reset Timing
        1. 8.7.1.1 Reset Timing
      2. 8.7.2  Clock Specifications
        1. 8.7.2.1 DCO in External Resistor Mode
        2. 8.7.2.2 DCO in Internal Resistor Mode
        3. 8.7.2.3 DCO Overall Tolerance Table
        4. 8.7.2.4 DCO in Bypass Mode Recommended Operating Conditions
      3. 8.7.3  Wake-up Characteristics
        1. 8.7.3.1 Wake-up Times From Low Power Modes
      4. 8.7.4  I/O Ports
        1. 8.7.4.1 Schmitt-Trigger Inputs – General-Purpose I/O
        2. 8.7.4.2 Inputs – Ports P1 and P2
        3. 8.7.4.3 Leakage Current – General-Purpose I/O
        4. 8.7.4.4 Outputs – General-Purpose I/O
        5. 8.7.4.5 Output Frequency – General-Purpose I/O
        6. 8.7.4.6 Typical Characteristics – Outputs
      5. 8.7.5  Power Management Module
        1. 8.7.5.1 PMM, High-Side Brownout Reset (BORH)
        2. 8.7.5.2 PMM, Low-Side SVS (SVSL)
        3. 8.7.5.3 PMM, Core Voltage
        4. 8.7.5.4 PMM, Voltage Monitor (VMON)
      6. 8.7.6  Reference Module
        1. 8.7.6.1 Voltage Reference (REF)
        2. 8.7.6.2 Temperature Sensor
      7. 8.7.7  SD24
        1. 8.7.7.1 SD24 Power Supply and Recommended Operating Conditions
        2. 8.7.7.2 SD24 Internal Voltage Reference
        3. 8.7.7.3 SD24 External Voltage Reference
        4. 8.7.7.4 SD24 Input Range
        5. 8.7.7.5 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
        6. 8.7.7.6 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
        7. 8.7.7.7 Typical Characteristics
      8. 8.7.8  eUSCI
        1. 8.7.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.7.8.2 eUSCI (UART Mode) Deglitch Characteristics
        3. 8.7.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.7.8.4 eUSCI (SPI Master Mode) Timing
        5. 8.7.8.5 eUSCI (SPI Slave Mode) Timing
        6. 8.7.8.6 eUSCI (I2C Mode) Timing
      9. 8.7.9  Timer_A
        1. 8.7.9.1 Timer_A
      10. 8.7.10 Flash
        1. 8.7.10.1 Flash Memory
      11. 8.7.11 Emulation and Debug
        1. 8.7.11.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Functional Block Diagrams
    3. 9.3  CPU
    4. 9.4  Instruction Set
    5. 9.5  Operating Modes
    6. 9.6  Interrupt Vector Addresses
    7. 9.7  Special Function Registers
    8. 9.8  Flash Memory
    9. 9.9  JTAG Operation
      1. 9.9.1 JTAG Standard Interface
      2. 9.9.2 Spy-Bi-Wire Interface
      3. 9.9.3 JTAG Disable Register
    10. 9.10 Peripherals
      1. 9.10.1 Clock System
      2. 9.10.2 Power-Management Module (PMM)
      3. 9.10.3 Digital I/O
      4. 9.10.4 Watchdog Timer (WDT)
      5. 9.10.5 Timer TA0
      6. 9.10.6 Timer TA1
      7. 9.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
      8. 9.10.8 Hardware Multiplier
      9. 9.10.9 SD24
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 9.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
      3. 9.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
      4. 9.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptor
    13. 9.13 Memory
      1. 9.13.1 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Device Identification
      2. 9.14.2 JTAG Identification
  10. 10Applications, Implementation, and Layout
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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9.13.1 Peripheral File Map

Table 9-17 lists the peripherals that support word access, and Table 9-18 lists the peripherals that support byte access. Peripherals that support both access types are listed in both tables.

Table 9-17 Peripherals With Word Access
MODULEREGISTER DESCRIPTIONACRONYMADDRESS
SYSJTAG disable registerSYSJTAGDIS0x01FE
Timer TA1Capture/compare register 2TA1CCR20x0196
Capture/compare register 1TA1CCR10x0194
Capture/compare register 0TA1CCR00x0192
Timer_A registerTA1R0x0190
Capture/compare control 2TA1CCTL20x0186
Capture/compare control 1TA1CCTL10x0184
Capture/compare control 0TA1CCTL00x0182
Timer_A controlTA1CTL0x0180
Timer_A interrupt vectorTA1IV0x011E
Timer TA0Capture/compare register 2TA0CCR20x0176
Capture/compare register 1TA0CCR10x0174
Capture/compare register 0TA0CCR00x0172
Timer_A registerTA0R0x0170
Capture/compare control 2TA0CCTL20x0166
Capture/compare control 1TA0CCTL10x0164
Capture/compare control 0TA0CCTL00x0162
Timer_A controlTA0CTL0x0160
Timer_A interrupt vectorTA0IV0x012E
eUSCI_A0USCI_A control word 0UCA0CTLW00x0140
USCI _A control word 1UCA0CTLW10x0142
USCI_A baud rate 0UCA0BR00x0146
USCI_A baud rate 1UCA0BR10x0147
USCI_A modulation controlUCA0MCTLW0x0148
USCI_A statusUCA0STAT0x014A
USCI_A receive bufferUCA0RXBUF0x014C
USCI_A transmit bufferUCA0TXBUF0x014E
USCI_A LIN controlUCA0ABCTL0x0150
USCI_A IrDA transmit controlUCA0IRTCTL0x0152
USCI_A IrDA receive controlUCA0IRRCTL0x0153
USCI_A interrupt enableUCA0IE0x015A
USCI_A interrupt flagsUCA0IFG0x015C
USCI_A interrupt vector wordUCA0IV0x015E
eUSCI_B0USCI_B control word 0UCB0CTLW00x01C0
USCI_B control word 1UCB0CTLW10x01C2
USCI_B bit rate 0UCB0BR00x01C6
USCI_B bit rate 1UCB0BR10x01C7
USCI_B status wordUCB0STATW0x01C8
USCI_B byte counter thresholdUCB0TBCNT0x01CA
USCI_B receive bufferUCB0RXBUF0x01CC
USCI_B transmit bufferUCB0TXBUF0x01CE
USCI_B I2C own address 0UCB0I2COA00x01D4
USCI_B I2C own address 1UCB0I2COA10x01D6
USCI_B I2C own address 2UCB0I2COA20x01D8
USCI_B I2C own address 3UCB0I2COA30x01DA
USCI_B received addressUCB0ADDRX0x01DC
USCI_B address maskUCB0ADDMASK0x01DE
USCI I2C slave addressUCB0I2CSA0x01E0
USCI interrupt enableUCB0IE0x01EA
USCI interrupt flagsUCB0IFG0x01EC
USCI interrupt vector wordUCB0IV0x01EE
Hardware MultiplierSum extendSUMEXT0x013E
Result high wordRESHI0x013C
Result low wordRESLO0x013A
Second operandOP20x0138
Multiply signed + accumulate/operand 1MACS0x0136
Multiply + accumulate/operand 1MAC0x0134
Multiply signed/operand 1MPYS0x0132
Multiply unsigned/operand 1MPY0x0130
Flash MemoryFlash control 3FCTL30x012C
Flash control 2FCTL20x012A
Flash control 1FCTL10x0128
Watchdog TimerWatchdog/timer controlWDTCTL0x0120
SD24
(also see Table 9-18)		SD24 interrupt vector word registerSD24IV0x01F0
Channel 3 conversion memory(1)(2)SD24MEM30x0116
Channel 2 conversion memory(2)SD24MEM20x0114
Channel 1 conversion memorySD24MEM10x0112
Channel 0 conversion memorySD24MEM00x0110
Channel 3 control(1)(2)SD24CCTL30x0108
Channel 2 control(2)SD24CCTL20x0106
Channel 1 controlSD24CCTL10x0104
Channel 0 controlSD24CCTL00x0102
General ControlSD24CTL0x0100
(1) Not available on MSP430i2031 and MSP430i2030 devices.
(2) Not available on MSP430i2021 and MSP430i2020 devices.
Table 9-18 Peripherals With Byte Access
MODULEREGISTER DESCRIPTIONREGISTER NAMEADDRESS
SD24
(also see Table 9-17)		SD24 trimSD24TRIM0x00BF
Channel 3 preload(1)(2)SD24PRE30x00BB
Channel 2 preload(2)SD24PRE20x00BA
Channel 1 preloadSD24PRE10x00B9
Channel 0 preloadSD24PRE00x00B8
Channel 3 input control(1)(2)SD24INCTL30x00B3
Channel 2 input control(2)SD24INCTL20x00B2
Channel 1 input controlSD24INCTL10x00B1
Channel 0 input controlSD24INCTL00x00B0
PMMReference calibration 1REFCAL10x0063
Reference calibration 0REFCAL00x0062
Voltage monitor controlVMONCTL0x0061
LPM4.5 controlLPM45CTL0x0060
Clock SystemClock system external resistor temperature calibrationCSERTCAL0x0055
Clock system external resistor frequency calibrationCSERFCAL0x0054
Clock system internal resistor temperature calibrationCSIRTCAL0x0053
Clock system internal resistor frequency calibrationCSIRFCAL0x0052
Clock system control 1CSCTL10x0051
Clock system control 0CSCTL00x0050
Port P2Port P2 interrupt flagP2IFG0x002D
Port P2 interrupt enableP2IE0x002B
Port P2 interrupt edge selectP2IES0x0029
Port P2 interrupt vector wordP2IV0x002E
Port P2 selection 1P2SEL10x001D
Port P2 selection 0P2SEL00x001B
Port P2 directionP2DIR0x0015
Port P2 outputP2OUT0x0013
Port P2 inputP2IN0x0011
Port P1Port P1 interrupt flagP1IFG0x002C
Port P1 interrupt enableP1IE0x002A
Port P1 interrupt edge selectP1IES0x0028
Port P1 interrupt vector wordP1IV0x001E
Port P1 selection 1P1SEL10x001C
Port P1 selection 0P1SEL00x001A
Port P1 directionP1DIR0x0014
Port P1 outputP1OUT0x0012
Port P1 inputP1IN0x0010
Special FunctionSFR interrupt flag 1IFG10x0002
SFR interrupt enable 1IE10x0000
(1) Not available on MSP430i2031 or MSP430i2030 devices.
(2) Not available on MSP430i2021 or MSP430i2020 devices.
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