ZHCSI49C September   2014  – March 2021

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
    3. 7.3 Pin Multiplexing
    4. 7.4 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Active Mode Supply Current (Into VCC) Excluding External Current
    5. 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6 Thermal Resistance Characteristics
    7. 8.7 Timing and Switching Characteristics
      1. 8.7.1  Reset Timing
        1. 8.7.1.1 Reset Timing
      2. 8.7.2  Clock Specifications
        1. 8.7.2.1 DCO in External Resistor Mode
        2. 8.7.2.2 DCO in Internal Resistor Mode
        3. 8.7.2.3 DCO Overall Tolerance Table
        4. 8.7.2.4 DCO in Bypass Mode Recommended Operating Conditions
      3. 8.7.3  Wake-up Characteristics
        1. 8.7.3.1 Wake-up Times From Low Power Modes
      4. 8.7.4  I/O Ports
        1. 8.7.4.1 Schmitt-Trigger Inputs – General-Purpose I/O
        2. 8.7.4.2 Inputs – Ports P1 and P2
        3. 8.7.4.3 Leakage Current – General-Purpose I/O
        4. 8.7.4.4 Outputs – General-Purpose I/O
        5. 8.7.4.5 Output Frequency – General-Purpose I/O
        6. 8.7.4.6 Typical Characteristics – Outputs
      5. 8.7.5  Power Management Module
        1. 8.7.5.1 PMM, High-Side Brownout Reset (BORH)
        2. 8.7.5.2 PMM, Low-Side SVS (SVSL)
        3. 8.7.5.3 PMM, Core Voltage
        4. 8.7.5.4 PMM, Voltage Monitor (VMON)
      6. 8.7.6  Reference Module
        1. 8.7.6.1 Voltage Reference (REF)
        2. 8.7.6.2 Temperature Sensor
      7. 8.7.7  SD24
        1. 8.7.7.1 SD24 Power Supply and Recommended Operating Conditions
        2. 8.7.7.2 SD24 Internal Voltage Reference
        3. 8.7.7.3 SD24 External Voltage Reference
        4. 8.7.7.4 SD24 Input Range
        5. 8.7.7.5 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
        6. 8.7.7.6 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
        7. 8.7.7.7 Typical Characteristics
      8. 8.7.8  eUSCI
        1. 8.7.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.7.8.2 eUSCI (UART Mode) Deglitch Characteristics
        3. 8.7.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.7.8.4 eUSCI (SPI Master Mode) Timing
        5. 8.7.8.5 eUSCI (SPI Slave Mode) Timing
        6. 8.7.8.6 eUSCI (I2C Mode) Timing
      9. 8.7.9  Timer_A
        1. 8.7.9.1 Timer_A
      10. 8.7.10 Flash
        1. 8.7.10.1 Flash Memory
      11. 8.7.11 Emulation and Debug
        1. 8.7.11.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Functional Block Diagrams
    3. 9.3  CPU
    4. 9.4  Instruction Set
    5. 9.5  Operating Modes
    6. 9.6  Interrupt Vector Addresses
    7. 9.7  Special Function Registers
    8. 9.8  Flash Memory
    9. 9.9  JTAG Operation
      1. 9.9.1 JTAG Standard Interface
      2. 9.9.2 Spy-Bi-Wire Interface
      3. 9.9.3 JTAG Disable Register
    10. 9.10 Peripherals
      1. 9.10.1 Clock System
      2. 9.10.2 Power-Management Module (PMM)
      3. 9.10.3 Digital I/O
      4. 9.10.4 Watchdog Timer (WDT)
      5. 9.10.5 Timer TA0
      6. 9.10.6 Timer TA1
      7. 9.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
      8. 9.10.8 Hardware Multiplier
      9. 9.10.9 SD24
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 9.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
      3. 9.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
      4. 9.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptor
    13. 9.13 Memory
      1. 9.13.1 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Device Identification
      2. 9.14.2 JTAG Identification
  10. 10Applications, Implementation, and Layout
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.2 Signal Descriptions

Section 7.2 describes the signals for all device variants and package options.

Table 7-1 Signal Descriptions
TERMINAL I/O(1) DESCRIPTION
NAME NO.(2)
PW RHB
A0.0+ 1 1 I SD24 positive analog input A0.0(3)
A0.0- 2 2 I SD24 negative analog input A0.0(3)
A1.0+ 3 3 I SD24 positive analog input A1.0(3)
A1.0- 4 4 I SD24 negative analog input A1.0(3)
A2.0+ 5 5 I SD24 positive analog input A2.0(3)(4)
A2.0- 6 6 I SD24 negative analog input A2.0(3)(4)
A3.0+ 7 7 I SD24 positive analog input A3.0 (3)(4)(5)
A3.0- 8 8 I SD24 negative analog input A3.0 (3)(4)(5)
VREF(6) 9 9 I SD24 external reference voltage input
AVSS 10 10 Analog supply voltage, negative terminal
ROSC 11 11 External resistor pin for DCO.

Connect recommended resistor between ROSC and AVSS for DCO operation in external resistor mode. Connect ROSC to AVSS while operating DCO in internal resistor mode.
DVSS 12 12 Digital supply voltage, negative terminal
VCC 13 13 Analog and digital supply voltage, positive terminal
VCORE (7) 14 14 Regulated core power supply (internal use only, no external current loading)
RST/NMI/SBWTDIO 15 15 I/O Reset or nonmaskable interrupt input.

Spy-Bi-Wire test data input/output for device programming and test.
TEST/SBWTCK 16 16 I Selects test mode for JTAG pins on P1.0 to P1.3.

Spy-Bi-Wire test clock input for device programming and test.
P1.0/UCA0STE/MCLK/TCK 17 17 I/O General-purpose digital I/O pin.

eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI).

MCLK output.

JTAG test clock. TCK is the clock input port for device programming and test.
P1.1/UCA0CLK/SMCLK/TMS 18 18 I/O General-purpose digital I/O pin.

eUSCI_A0 clock input/output (direction controlled by eUSCI).

SMCLK output.

JTAG test mode select. TMS is used as an input port for device programming and test.
P1.2/UCA0RXD/UCA0SOMI/ ACLK/TDI/TCLK 19 19 I/O General-purpose digital I/O pin.

eUSCI_A0 UART receive data or eUSCI_A0 SPI slave out/master in (direction controlled by eUSCI).

ACLK output.

JTAG test data input or test clock input for device programming and test.
P1.3/UCA0TXD/UCA0SIMO/ TA0CLK/TDO/TDI 20 20 I/O General-purpose digital I/O pin.

eUSCI_A0 UART transmit data or eUSCI_A0 SPI slave in/master out (direction controlled by eUSCI).

Timer external clock input TACLK for TA0.

JTAG test data output port. TDO/TDI data output or programming data input terminal.
P1.4/UCB0STE/TA0.0 21 21 I/O General-purpose digital I/O pin.

eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI).

Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output.
P1.5/UCB0CLK/TA0.1 22 22 I/O General-purpose digital I/O pin.

eUSCI_B0 clock input/output (direction controlled by eUSCI).

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output.
P1.6/UCB0SCL/UCB0SOMI/ TA0.2 23 23 I/O General-purpose digital I/O pin.

eUSCI_B0 I2C clock or eUSCI_B0 SPI slave out/master in (direction controlled by eUSCI).

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output.
P1.7/UCB0SDA/UCB0SIMO/ TA1CLK 24 24 I/O General-purpose digital I/O pin.

eUSCI_B0 I2C data or eUSCI_B0 slave input/master output (direction controlled by eUSCI).

Timer external clock input TACLK for TA1.
P2.0/TA1.0/CLKIN 25 25 I/O General-purpose digital I/O pin.

Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output.

DCO bypass clock input.
P2.1/TA1.1 26 26 I/O General-purpose digital I/O pin.

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output.
P2.2/TA1.2 27 27 I/O General-purpose digital I/O pin.

Timer TA1 CCR2 capture: CCI2A input, compare: Out2 output.
P2.3/VMONIN 28 28 I/O General-purpose digital I/O pin.

Voltage monitor input.
P2.4/TA1.0(8) N/A 29 I/O General-purpose digital I/O pin.

Timer TA1 CCR0 capture: CCI0B input, compare: Out0 output.
P2.5/TA0.0(8) N/A 30 I/O General-purpose digital I/O pin.

Timer TA0 CCR0 capture: CCI0B input, compare: Out0 output.
P2.6/TA0.1(8) N/A 31 I/O General-purpose digital I/O pin.

Timer TA0 CCR1 compare: Out1 output.
P2.7/TA0.2(8) N/A 32 I/O General-purpose digital I/O pin.

Timer TA0 CCR2 compare: Out2 output.
(1) I = input, O = output
(2) N/A = not available
(3) Short unused analog input pairs and connect them to analog ground (see Section 7.4 for recommendations on all unused pins).
(4) Not available on MSP430i2021 and MSP430i2020 devices.
(5) Not available on MSP430i2031 and MSP430i2030 devices.
(6) When the SD24 operates with the internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Connect only the recommended capacitor value (CVREF) from the VREF pin to AVSS (see Section 8.7.7.2).
(7) VCORE is for internal use only. No external current loading is possible. Connect VCORE to only the recommended capacitor value (CVCORE) (see Section 8.3).
(8) These pins are not available on the 28-pin PW package. Program these four pins to output direction and drive value 0 in software.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |