6.4.1 SRAM

The MSP432E411Y MCU provides 256KB of single-cycle on-chip SRAM. The internal SRAM of the device is at offset 0x2000.0000 of the device memory map.

The SRAM is implemented using four 32-bit-wide interleaving SRAM banks (separate SRAM arrays), which allow for increased speed between memory accesses. The SRAM memory provides nearly 2 GBps of memory bandwidth at a 120-MHz clock frequency.

Because read-modify-write (RMW) operations are time consuming, Arm has introduced bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in an atomic operation.

Data can be transferred to and from SRAM by the following masters:

• µDMA
• USB
• LCD controller
• Ethernet controller