The CPU subsystem (MCPUSS) implements an Arm Cortex-M0+ CPU, a system timer, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized 32-bit CPU that delivers high performance and low power to embedded applications. Key features of the CPU Sub System include:

• Arm Cortex-M0+ CPU supports clock frequencies from 32kHz to 24MHz
  • ARMv6-M Thumb instruction set (little endian) with 32-cycle 32x32 slow multiply instruction
• Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining