ZHCS399E August   2011  – January 2017 OMAP-L132

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
      1. Table 3-4 OMAP-L132 Top Level Memory Map
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Pin Multiplexing Control
    8. 3.8 Terminal Functions
      1. 3.8.1  Device Reset, NMI and JTAG
      2. 3.8.2  High-Frequency Oscillator and PLL
      3. 3.8.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.8.4  DEEPSLEEP Power Control
      5. 3.8.5  External Memory Interface A (EMIFA)
      6. 3.8.6  DDR2/mDDR Controller
      7. 3.8.7  Serial Peripheral Interface Modules (SPI)
      8. 3.8.8  Programmable Real-Time Unit (PRU)
      9. 3.8.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.8.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.8.11 Boot
      12. 3.8.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.8.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.8.14 Timers
      15. 3.8.15 Multichannel Audio Serial Ports (McASP)
      16. 3.8.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.8.17 Universal Serial Bus Modules (USB0)
      18. 3.8.18 Ethernet Media Access Controller (EMAC)
      19. 3.8.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.8.20 General Purpose Input Output
      21. 3.8.21 Reserved and No Connect
      22. 3.8.22 Supply and Ground
    9. 3.9 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
      2. 6.7.2 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-21 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-22 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-23 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-42 Timing Requirements for MMC/SD (see and )
        2. Table 6-43 Switching Characteristics for MMC/SD (see through )
    14. 6.14 Multichannel Audio Serial Port (McASP)
      1. 6.14.1 McASP Peripheral Registers Description(s)
      2. 6.14.2 McASP Electrical Data/Timing
        1. 6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 Timing Requirements for McASP0 (1.2V, 1.1V)
          2. Table 6-48 Timing Requirements for McASP0 (1.0V)
          3. Table 6-49 Switching Characteristics for McASP0 (1.2V, 1.1V)
          4. Table 6-50 Switching Characteristics for McASP0 (1.0V)
    15. 6.15 Multichannel Buffered Serial Port (McBSP)
      1. 6.15.1 McBSP Peripheral Register Description(s)
      2. 6.15.2 McBSP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-52 Timing Requirements for McBSP0 [1.2V, 1.1V] (see )
          2. Table 6-53 Timing Requirements for McBSP0 [1.0V] (see )
          3. Table 6-54 Switching Characteristics for McBSP0 [1.2V, 1.1V] (see )
          4. Table 6-55 Switching Characteristics for McBSP0 [1.0V] (see )
          5. Table 6-56 Timing Requirements for McBSP1 [1.2V, 1.1V] (see )
          6. Table 6-57 Timing Requirements for McBSP1 [1.0V] (see )
          7. Table 6-58 Switching Characteristics for McBSP1 [1.2V, 1.1V] (see )
          8. Table 6-59 Switching Characteristics for McBSP1 [1.0V] (see )
          9. Table 6-60 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
          10. Table 6-61 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    16. 6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.16.1 SPI Peripheral Registers Description(s)
      2. 6.16.2 SPI Electrical Data/Timing
        1. 6.16.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-63 General Timing Requirements for SPI0 Master Modes
          2. Table 6-64 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-71 General Timing Requirements for SPI1 Master Modes
          4. Table 6-72 General Timing Requirements for SPI1 Slave Modes
          5. Table 6-73 Additional SPI1 Master Timings, 4-Pin Enable Option
          6. Table 6-74 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    17. 6.17 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.17.1 I2C Device-Specific Information
      2. 6.17.2 I2C Peripheral Registers Description(s)
      3. 6.17.3 I2C Electrical Data/Timing
        1. 6.17.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-80 Timing Requirements for I2C Input
          2. Table 6-81 Switching Characteristics for I2C
    18. 6.18 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.18.1 UART Peripheral Registers Description(s)
      2. 6.18.2 UART Electrical Data/Timing
        1. Table 6-83 Timing Requirements for UART Receive (see )
        2. Table 6-84 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    19. 6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.19.1 USB0 [USB2.0] Electrical Data/Timing
        1. Table 6-86 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
    20. 6.20 Ethernet Media Access Controller (EMAC)
      1. 6.20.1 EMAC Peripheral Register Description(s)
        1. 6.20.1.1 EMAC Electrical Data/Timing
          1. Table 6-91 Timing Requirements for MII_RXCLK (see )
          2. Table 6-92 Timing Requirements for MII_TXCLK (see )
          3. Table 6-93 Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
          4. Table 6-94 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
    21. 6.21 Management Data Input/Output (MDIO)
      1. 6.21.1 MDIO Register Description(s)
      2. 6.21.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-98 Timing Requirements for MDIO Input (see and )
        2. Table 6-99 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    22. 6.22 Enhanced Capture (eCAP) Peripheral
      1. Table 6-101 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-102 Switching Characteristics Over Recommended Operating Conditions for eCAP
    23. 6.23 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.23.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-104 Timing Requirements for eHRPWM
        2. Table 6-105 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.23.2 Trip-Zone Input Timing
    24. 6.24 Timers
      1. 6.24.1 Timer Electrical Data/Timing
        1. Table 6-107 Timing Requirements for Timer Input (see )
        2. Table 6-108 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    25. 6.25 Real Time Clock (RTC)
      1. 6.25.1 Clock Source
      2. 6.25.2 Real-Time Clock Register Descriptions
    26. 6.26 General-Purpose Input/Output (GPIO)
      1. 6.26.1 GPIO Register Description(s)
      2. 6.26.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-111 Timing Requirements for GPIO Inputs (see )
        2. Table 6-112 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.26.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-113 Timing Requirements for External Interrupts (see )
    27. 6.27 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.27.1 PRUSS Register Descriptions
    28. 6.28 Emulation Logic
      1. 6.28.1 JTAG Port Description
      2. 6.28.2 Scan Chain Configuration Parameters
      3. 6.28.3 Initial Scan Chain Configuration
        1. 6.28.3.1 Adding TAPS to the Scan Chain
      4. 6.28.4 IEEE 1149.1 JTAG
        1. 6.28.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.28.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-125 Timing Requirements for JTAG Test Port (see )
          2. Table 6-126 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.28.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 出口管制提示
    8. 7.8 术语表
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZWT Package
    2. 8.2 Packaging Information

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机械数据 (封装 | 引脚)
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6.26.1 GPIO Register Description(s)

Table 6-110 GPIO Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 6000 REV Peripheral Revision Register
0x01E2 6004 RESERVED Reserved
0x01E2 6008 BINTEN GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
0x01E2 6010 DIR01 GPIO Banks 0 and 1 Direction Register
0x01E2 6014 OUT_DATA01 GPIO Banks 0 and 1 Output Data Register
0x01E2 6018 SET_DATA01 GPIO Banks 0 and 1 Set Data Register
0x01E2 601C CLR_DATA01 GPIO Banks 0 and 1 Clear Data Register
0x01E2 6020 IN_DATA01 GPIO Banks 0 and 1 Input Data Register
0x01E2 6024 SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
0x01E2 6028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
0x01E2 602C SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
0x01E2 6030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
0x01E2 6034 INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register
GPIO Banks 2 and 3
0x01E2 6038 DIR23 GPIO Banks 2 and 3 Direction Register
0x01E2 603C OUT_DATA23 GPIO Banks 2 and 3 Output Data Register
0x01E2 6040 SET_DATA23 GPIO Banks 2 and 3 Set Data Register
0x01E2 6044 CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register
0x01E2 6048 IN_DATA23 GPIO Banks 2 and 3 Input Data Register
0x01E2 604C SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
0x01E2 6050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
0x01E2 6054 SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
0x01E2 6058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
0x01E2 605C INTSTAT23 GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
0x01E2 6060 DIR45 GPIO Banks 4 and 5 Direction Register
0x01E2 6064 OUT_DATA45 GPIO Banks 4 and 5 Output Data Register
0x01E2 6068 SET_DATA45 GPIO Banks 4 and 5 Set Data Register
0x01E2 606C CLR_DATA45 GPIO Banks 4 and 5 Clear Data Register
0x01E2 6070 IN_DATA45 GPIO Banks 4 and 5 Input Data Register
0x01E2 6074 SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
0x01E2 607C SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
0x01E2 6080 CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
0x01E2 6084 INTSTAT45 GPIO Banks 4 and 5 Interrupt Status Register
GPIO Banks 6 and 7
0x01E2 6088 DIR67 GPIO Banks 6 and 7 Direction Register
0x01E2 608C OUT_DATA67 GPIO Banks 6 and 7 Output Data Register
0x01E2 6090 SET_DATA67 GPIO Banks 6 and 7 Set Data Register
0x01E2 6094 CLR_DATA67 GPIO Banks 6 and 7 Clear Data Register
0x01E2 6098 IN_DATA67 GPIO Banks 6 and 7 Input Data Register
0x01E2 609C SET_RIS_TRIG67 GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
0x01E2 60A0 CLR_RIS_TRIG67 GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
0x01E2 60A8 CLR_FAL_TRIG67 GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
0x01E2 60AC INTSTAT67 GPIO Banks 6 and 7 Interrupt Status Register
GPIO Bank 8
0x01E2 60B0 DIR8 GPIO Bank 8 Direction Register
0x01E2 60B4 OUT_DATA8 GPIO Bank 8 Output Data Register
0x01E2 60B8 SET_DATA8 GPIO Bank 8 Set Data Register
0x01E2 60BC CLR_DATA8 GPIO Bank 8 Clear Data Register
0x01E2 60C0 IN_DATA8 GPIO Bank 8 Input Data Register
0x01E2 60C4 SET_RIS_TRIG8 GPIO Bank 8 Set Rising Edge Interrupt Register
0x01E2 60C8 CLR_RIS_TRIG8 GPIO Bank 8 Clear Rising Edge Interrupt Register
0x01E2 60CC SET_FAL_TRIG8 GPIO Bank 8 Set Falling Edge Interrupt Register
0x01E2 60D0 CLR_FAL_TRIG8 GPIO Bank 8 Clear Falling Edge Interrupt Register
0x01E2 60D4 INTSTAT8 GPIO Bank 8 Interrupt Status Register
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