SLLS910A July 2008 – June 2016 ONET8501PB
PRODUCTION DATA.
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| COC1 | 5 | Analog | Offset cancellation filter capacitor plus terminal. An external capacitor can be connected between this pin and COC2 to reduce the low frequency cutoff. To disable the offset cancellation loop, connect COC1 and COC2 together. |
| COC2 | 6 | Analog | Offset cancellation filter capacitor minus terminal. An external capacitor can be connected between this pin and COC1 to reduce the low frequency cutoff. To disable the offset cancellation loop, connect COC1 and COC2 together. |
| DIN+ | 2 | Analog-input | Noninverted data input. Differentially 100 Ω terminated to DIN–. |
| DIN– | 3 | Analog-input | Inverted data input. Differentially 100 Ω terminated to DIN+. |
| DIS | 7 | Digital-input | Disables the output stage when set to a high level. |
| DOUT– | 10 | CML-out | Inverted data output. On-chip 50 Ω back-terminated to VCC. |
| DOUT+ | 11 | CML-out | Noninverted data output. On-chip 50 Ω back-terminated to VCC. |
| GND | 1,4, EP | Supply | Circuit ground. Exposed die pad (EP) must be grounded. |
| LOS | 8 | Open-drain MOS | High level indicates that the input signal amplitude is below the programmed threshold level. Open-drain output. Requires an external 10-kΩ pullup resistor to VCC for proper operation. |
| RATE1 | 13 | Digital-input | Bandwidth selection for noise suppression. |
| RATE0 | 14 | Digital-input | Bandwidth selection for noise suppression. |
| SCK | 15 | Digital-input | Serial interface clock input. Connect a pullup resistor (10 kΩ typical) to VCC. |
| SDA | 16 | Digital-input | Serial interface data input. Connect a pullup resistor (10 kΩ typical) to VCC. |
| VCC | 9, 12 | Supply | 3.3-V ± 10% supply voltage. |