ZHCSRO1A february 2023 – july 2023 OPA1633
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- DGN|8
订购信息
5 Pin Configuration and Functions
Figure 5-1 D Package, 8-Pin SOIC or DGN(1) Package, 8-Pin HVSSOP
(Top View)
Table 5-1 Pin Functions
| PIN | TYPE(2) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| Enable | 7 | I | Active-high enable pin |
| V+ | 3 | I/O | Positive supply voltage pin |
| V- | 6 | I/O | Negative supply voltage pin |
| IN+ | 8 | I | Positive input voltage pin |
| IN– | 1 | I | Negative input voltage pin |
| VOCM | 2 | I | Output common-mode control voltage pin |
| OUT+ | 4 | O | Positive output voltage pin |
| OUT– | 5 | O | Negative output voltage pin |
(1) Solder the exposed DGN package thermal pad to a heat-spreading
power or ground plane. This pad is electrically isolated from the die, but must
be connected to a power or ground plane and not floated.
(2) I = input, O = output.