ZHCS618B December   2011  – December 2016 OPA1652 , OPA1654

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA1652
    5. 6.5 Thermal Information: OPA1654
    6. 6.6 Electrical Characteristics: VS = ±15 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Phase Reversal Protection
      2. 7.3.2 Input Protection
      3. 7.3.3 Electrical Overstress
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Voltage
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Performance
      2. 8.1.2 Total Harmonic Distortion Measurements
      3. 8.1.3 Capacitive Loads
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 TINA-TI™（免费软件下载）
        2. 11.1.1.2 DIP 适配器 EVM
        3. 11.1.1.3 通用运算放大器评估模块 (EVM)
        4. 11.1.1.4 智能放大器扬声器特性鉴定板评估模块
        5. 11.1.1.5 TI 高精度设计
        6. 11.1.1.6 WEBENCH滤波器设计器
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 相关链接
    4. 11.4 接收文档更新通知
    5. 11.5 社区资源
    6. 11.6 商标
    7. 11.7 静电放电警告
    8. 11.8 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

OPA1652 D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OPA1652 OPA1654 DAPPER_Dual_DIP.gif
OPA1652 DRG Package
8-Pin WSON With Exposed Thermal Pad
Top View
OPA1652 OPA1654 SBOS477_DRG_Dual_Package.gif

Pin Functions: OPA1652

PIN I/O DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
+IN A 3 I Noninverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Noninverting input, channel B
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
V– 4 — Negative (lowest) power supply
V+ 8 — Positive (highest) power supply
Thermal pad — — Exposed thermal die pad on underside of DRG package; connect thermal die pad to V–. Soldering the thermal pad improves heat dissipation and provides specified performance
OPA1654 D and PW Packages
14-Pin SOIC and TSSOP
Top View
OPA1652 OPA1654 DAPPER_Quad_DIP.gif

Pin Functions: OPA1654

PIN I/O DESCRIPTION
NAME NO.
–IN A 2 I Inverting input, channel A
+IN A 3 I Noninverting input, channel A
–IN B 6 I Inverting input, channel B
+IN B 5 I Noninverting input, channel B
–IN C 9 I Inverting input, channel C
+IN D 10 I Noninverting input, channel C
–IN D 13 I Inverting input, channel D
+IN D 12 I Noninverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V– 11 — Negative (lowest) power supply
V+ 4 — Positive (highest) power supply
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