SBOS426D November 2008 – October 2016 OPA209 , OPA2209 , OPA4209
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
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订购信息
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage | Supply voltage, VS = (V+) – (V–) | 40 | V | |
| Signal input pins(2) | (V–) – 0.5 | (V+) + 0.5 | V | |
| Current | Signal input pins(2) | –10 | 10 | mA |
| Output short circuit(3) | Continuous | |||
| Temperature | Operating, TA | –55 | 150 | °C |
| Junction, TJ | 200 | °C | ||
| Storage, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For input voltages beyond the power-supply rails, voltage or current must be limited.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VS | Specified voltage | ±2.25 | ±18 | V |
| Specified temperature | –40 | 125 | °C | |
| TA | Operating temperature | –55 | 150 | °C |
6.4 Thermal Information: OPA209
| THERMAL METRIC(1) | OPA209 | UNIT | |||
|---|---|---|---|---|---|
| DBV (SOT-23) | D (SOIC) | DGK (VSSOP) | |||
| 5 PINS | 8 PINS | 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 204.9 | 135.5 | 142.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 200 | 73.7 | 46.9 | °C/W |
| RθJB | Junction-to-board thermal resistance | 113.1 | 61.9 | 63.5 | °C/W |
| ψJT | Junction-to-top characterization parameter | 38.2 | 19.7 | 5.3 | °C/W |
| ψJB | Junction-to-board characterization parameter | 104.9 | 54.8 | 62.8 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Thermal Information: OPA2209
| THERMAL METRIC(1) | OPA2209 | UNIT | ||
|---|---|---|---|---|
| D (SOIC) | DGK (VSSOP) | |||
| 8 PINS | 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 134.3 | 132.7 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 72.1 | 38.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 60.7 | 52.1 | °C/W |
| ψJT | Junction-to-top characterization parameter | 18.2 | 2.4 | °C/W |
| ψJB | Junction-to-board characterization parameter | 53.8 | 52.8 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.6 Thermal Information: OPA4209
| THERMAL METRIC(1) | OPA4209 | UNIT | |
|---|---|---|---|
| PW (TSSOP) | |||
| 14 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 112.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 26.1 | °C/W |
| RθJB | Junction-to-board thermal resistance | 61 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.7 | °C/W |
| ψJB | Junction-to-board characterization parameter | 59.2 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.7 Electrical Characteristics
at VS = ±2.25 V to ±18 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||||
|---|---|---|---|---|---|---|---|---|---|
| OFFSET VOLTAGE | |||||||||
| VOS | Input offset voltage | VS = ±15 V, VCM = 0 V | ±35 | ±150 | µV | ||||
| dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | 1 | 3 | µV/°C | ||||
| PSRR | vs power supply | VS = ±2.25 V to ±18 V | TA = 25°C | 0.05 | 0.5 | µV/V | |||
| TA = –40°C to 125°C | 1 | ||||||||
| Channel separation | DC (dual and quad versions) | 1 | µV/V | ||||||
| INPUT BIAS CURRENT | |||||||||
| IB | Input bias current | VCM = 0 V | TA = 25°C | ±1 | ±4.5 | nA | |||
| TA = –40°C to 85°C | ±8 | ||||||||
| TA = –40°C to 125°C | ±15 | ||||||||
| IOS | Input offset current | VCM = 0 V | TA = 25°C | ±0.7 | ±4.5 | nA | |||
| TA = –40°C to 85°C | ±8 | ||||||||
| TA = –40°C to 125°C | ±15 | ||||||||
| NOISE | |||||||||
| en | Input voltage noise | f = 0.1 Hz to 10 Hz | 0.13 | µVPP | |||||
| Noise density | f = 10 Hz | 3.3 | nV/√Hz | ||||||
| f = 100 Hz | 2.25 | ||||||||
| f = 1 kHz | 2.2 | ||||||||
| In | Input current noise density | f = 1 kHz | 500 | fA/√Hz | |||||
| INPUT VOLTAGE RANGE | |||||||||
| VCM | Common-mode voltage range | (V–) + 1.5 | (V+) – 1.5 | V | |||||
| CMRR | Common-mode rejection ratio | (V–) + 1.5 V < VCM < (V+) – 1.5 V, TA = –40°C to 125°C | 120 | 130 | dB | ||||
| INPUT IMPEDANCE | |||||||||
| Differential | 200 || 4 | kΩ || pF | |||||||
| Common-mode | 109 || 2 | Ω || pF | |||||||
| OPEN-LOOP GAIN | |||||||||
| AOL | Open-loop voltage gain | (V–) + 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ |
TA = 25°C | 126 | 132 | dB | |||
| TA = –40°C to 125°C | 120 | ||||||||
| (V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 600 Ω(1) |
TA = 25°C | 114 | 120 | ||||||
| TA = –40°C to 125°C | 110 | ||||||||
| FREQUENCY RESPONSE | |||||||||
| GBW | Gain bandwidth product | 18 | MHz | ||||||
| SR | Slew rate | 6.4 | V/µs | ||||||
| Φm | Phase margin | RL = 10 kΩ, CL = 25 pF | 80 | ° | |||||
| tS | Settling time | 0.1%, G = –1, 10-V step, CL = 100 pF | 2.1 | µs | |||||
| 0.0015% (16-bit), G = –1, 10-V step, CL = 100 pF | 2.6 | ||||||||
| Overload recovery time | G = –1 | < 1 | µs | ||||||
| THD+N | Total harmonic distortion + noise | G = +1, f = 1 kHz, VO = 20 VPP, 600 Ω | 0.000025% | ||||||
| OUTPUT | |||||||||
| Voltage output swing | RL = 10 kΩ, AOL > 130 dB | (V–) + 0.2 | (V+) – 0.2 | V | |||||
| RL = 600 Ω, AOL > 114 dB | (V–) + 0.6 | (V+) – 0.6 | |||||||
| RL = 10 kΩ, AOL > 120 dB, TA = –40°C to 125°C | (V–) + 0.2 | (V+) – 0.2 | |||||||
| ISC | Short-circuit current | VS = ±18 V | ±65 | mA | |||||
| CLOAD | Capacitive load drive (stable operation) |
See Typical Characteristics | |||||||
| ZO | Open-loop output impedance | See Typical Characteristics | |||||||
| POWER SUPPLY | |||||||||
| IQ | Quiescent current (per amplifier) |
IO = 0 A | TA = 25°C | 2.2 | 2.5 | mA | |||
| TA = –40°C to 125°C | 3.25 | ||||||||
(1) See Absolute Maximum Ratings for additional information.
6.8 Typical Characteristics
at TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Figure 1. Input Voltage Noise Density vs Frequency
Figure 3. Total Harmonic Distortion + Noise Ratiovs Frequency
Figure 5. 0.1-Hz to 10-Hz Noise
Figure 7. Common-Mode Rejection Ratiovs Frequency
Figure 9. Open-Loop Gain and Phase vs Frequency
Figure 11. Offset Voltage Production Distribution
vs Temperature
Figure 15. Input Offset Voltage vs Time
Figure 17. Input Bias and Input Offset Currentsvs Common-Mode Voltage
Figure 19. Quiescent Current vs Temperature
Figure 21. Short-Circuit Current vs Temperature
Figure 23. Small-Signal Step Response
Figure 25. Large-Signal Step Response
Figure 27. No Phase Reversal
Figure 29. Positive Overvoltage Recovery
Figure 4. Total Harmonic Distortion + Noise Ratiovs Amplitude
Figure 6. Power-Supply Rejection Ratiovs Frequency (Referred to Input)
Figure 8. Open-Loop Output Impedancevs Frequency
Figure 10. Open-Loop Gain vs Temperature
Figure 12. Offset Voltage Drift Production Distribution
Figure 14. Input Offset Voltagevs Common-Mode Voltage
Figure 16. Input Offset Current vs Supply Voltage
Figure 20. Quiescent Current vs Supply Voltage
Figure 22. Output Voltage vs Output Current
Figure 24. Small-Signal Step Response
Figure 26. Large-Signal Step Response
Figure 28. Negative Overload Recovery
Figure 30. Small-Signal Overshootvs Capacitive Load