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ZHCSIQ3B September 2018 – June 2019 OPA2156

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

D|8
- MSOI002K
DGK|8
- MPDS028E

散热焊盘机械数据 (封装 | 引脚)

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6.6 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION	FIGURE
Offset Voltage Production Distribution	Figure 1
Offset Voltage vs Temperature (PMOS)	Figure 2
Offset Voltage vs Temperature (NMOS)	Figure 3
Offset Voltage vs Power Supply	Figure 4
Offset Voltage vs Common-Mode Voltage	Figure 5
Offset Voltage vs Common-Mode Voltage in Transition Region	Figure 6
Offset Voltage Drift	Figure 7
Input Voltage Noise Spectral Density	Figure 8
0.1-Hz to 10-Hz Noise	Figure 9
THD+N vs Frequency	Figure 10
THD+N vs Output Amplitude	Figure 11
Input Bias and Offset Current vs Common-Mode Voltage	Figure 12
Input Bias and Offset Current vs Temperature	Figure 13
Input Bias and Offset Current vs Temperature	Figure 14
Open-Loop Output Impedance vs Frequency	Figure 15
Maximum Output Voltage vs Frequency	Figure 16
Open-Loop Gain and Phase Vs Frequency	Figure 17
Open-Loop Gain vs Temperature	Figure 18
Closed-Loop Gain vs Frequency	Figure 19
CMRR vs Frequency	Figure 20
PSRR vs Frequency	Figure 21
CMRR vs Temperature	Figure 22
PSRR vs Temperature	Figure 23
Positive Output Voltage vs Output Current	Figure 24
Negative Output Voltage vs Output Current	Figure 26
Short-Circuit Current vs Temperature	Figure 25
No Phase Reversal	Figure 27
Phase Margin vs Capacitive Load	Figure 28
Small-Signal Overshoot vs Capacitive Load (G = –1)	Figure 29
Small-Signal Overshoot vs Capacitive Load (G= +1)	Figure 30
Settling Time	Figure 31
Negative Overload Recovery	Figure 32
Positive Overload Recovery	Figure 33
Small-Signal Step Response (Noninverting)	Figure 34
Small-Signal Step Response (Inverting)	Figure 35
Large-Signal Step Response (Noninverting)	Figure 36
Large-Signal Step Response (Inverting)	Figure 37
Quiescent Current vs Supply Voltage	Figure 38
Quiescent Current vs Temperature	Figure 39
Channel Separation vs Frequency	Figure 40
EMIRR vs Frequency	Figure 41

at T_A = 25°C, V_S = ±18 V, V_CM = V_S / 2, R_L = 10 kΩ connected to V_S / 2, and C_L = 30 pF (unless otherwise noted)

OPA2156 D000_Vos distribution_18v_supply.gif

T_A = 25°C

Figure 1. Offset Voltage Production Distribution

NMOS region

Figure 3. Offset Voltage vs Temperature (NMOS)

Figure 5. Offset Voltage vs Common-Mode Voltage

T_A = –40°C to +125°C

Figure 7. Offset Voltage Drift

Figure 9. 0.1-Hz to 10-Hz Noise

OPA2156 D010_THDN_Vrms_2Configs_2Loads.gif

1 kHz, 80-kHz measurement bandwidth

Figure 11. THD+N vs Output Amplitude

T_A = –55°C to +85°C

Figure 13. Input Bias and Offset Current vs Temperature (SOIC)

OPA2156 D011_OpenLoopOutputImpedance.gif

Figure 15. Open-Loop Output Impedance vs Frequency

Figure 17. Open-Loop Gain and Phase vs Frequency

Figure 19. Closed-Loop Gain vs Frequency

OPA2156 D007B_PSRR_vs_Frequency_Updated.gif

Figure 21. PSRR vs Frequency

Figure 23. PSRR vs Temperature

Figure 25. Short-Circuit Current vs Temperature

Figure 27. No Phase Reversal

OPA2156 D031_Inverting_Overshoot_Vs_Capload.gif

10-mV output step, gain = –1

Figure 29. Small Signal Overshoot vs Capacitive Load


Vin = 5-Vpp

Figure 31. Normalized Settling Time


Gain = –10

Figure 33. Positive Overload Recovery


Vin = 10 mVpp, gain = –1

Figure 35. Small-Signal Step Response (Inverting)


Vin = 5 Vpp, gain = –1

Figure 37. Large Signal Step Response (Inverting)

Figure 39. Quiescent Current vs Temperature

Prf =-10 dBm

Figure 41. EMIRR vs Frequency

PMOS region

Figure 2. Offset Voltage vs Temperature (PMOS)

Figure 4. Offset Voltage vs Power Supply

OPA2156 D017A_Vos_vs_Vcm_Temp_TransitionNMOS.gif

Transition between PMOS and NMOS regions

Figure 6. Offset Voltage vs Common-Mode Voltage in Transition Region

Figure 8. Input Voltage Noise Spectral Density

OPA2156 D009_THDN_Freq_2Configs_2Loads_3p5Vrms.gif

3.5 V_RMS, 80-kHz measurement bandwidth

Figure 10. THD+N vs Frequency

Figure 12. Input Bias and Offset Current vs Common-Mode Voltage (SOIC)

T_A = –55°C to +125°C

Figure 14. Input Bias and Offset Current vs Temperature (SOIC)

Figure 16. Maximum Output Voltage vs Frequency

Figure 18. Open-Loop Gain vs Temperature

Figure 20. CMRR vs Frequency

Figure 22. CMRR vs Temperature

Figure 24. Positive Output Voltage vs Output Current

Figure 26. Negative Output Voltage vs Output Current

OPA2156 D005_PhaseMargin_vs_Cload_New.gif

Figure 28. Phase Margin vs Capacitive Load

OPA2156 D032_NonInverting_Overshoot_Vs_Capload.gif

10-mV output step, gain = +1

Figure 30. Small Signal Overshoot vs Capacitive Load


Gain = –10

Figure 32. Negative Overload Recovery


Vin = 10 mVpp, gain = 1

Figure 34. Small-Signal Step Response (Noninverting)


Vin = 5 Vpp, gain = 1

Figure 36. Large-Signal Step Response (Noninverting)

Figure 38. Quiescent Current vs Supply Voltage

OPA2156 D013_ChannelSeparation_Smooth.gif

Figure 40. Channel Separation vs Frequency