ZHCSFV2D December 2016 – December 2018 OPA187 , OPA2187 , OPA4187
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
DESCRIPTION | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 1 |
Offset Voltage Drift Distribution | Figure 2 |
Offset Voltage vs Temperature | Figure 3 |
Offset Voltage vs Common-Mode Voltage | Figure 4 |
Offset Voltage vs Power Supply | Figure 5 |
Open-Loop Gain and Phase vs Frequency | Figure 6 |
Closed-Loop Gain vs Frequency | Figure 7 |
IB vs Common-Mode Voltage | Figure 8 |
Input Bias Current vs Temperature | Figure 9 |
Output Voltage Swing vs Output Current | Figure 10 |
CMRR and PSRR vs Frequency (Referred-to-Input) | Figure 11 |
CMRR vs Temperature | Figure 12 |
PSRR vs Temperature | Figure 13 |
0.1-Hz to 10-Hz Noise | Figure 14 |
Input Voltage Noise Spectral Density vs Frequency | Figure 15 |
THD+N Ratio vs Frequency | Figure 16 |
THD+N vs Output Amplitude | Figure 17 |
Quiescent Current vs Supply Voltage | Figure 18 |
Quiescent Current vs Temperature | Figure 19 |
Open-Loop Gain vs Temperature | Figure 20 |
Open-Loop Output Impedance vs Frequency | Figure 21 |
Small-Signal Overshoot vs Capacitive Load (G = 1) (10-mV Output Step) | Figure 22 |
No Phase Reversal | Figure 23 |
Positive Overload Recovery | Figure 24 |
Negative Overload Recovery | Figure 25 |
Small-Signal Step Response (10 mV) | Figure 26, Figure 27 |
Large-Signal Step Response | Figure 28, Figure 29 |
Large-Signal Settling Time (10-V Positive Step) | Figure 30 |
Large-Signal Settling Time (10-V Negative Step) | Figure 31 |
Short-Circuit Current vs Temperature | Figure 32 |
Maximum Output Voltage vs Frequency | Figure 33 |
Crosstalk vs Frequency | Figure 34 |
EMIRR IN+ vs Frequency | Figure 35 |