米6体育平台手机版

ZHCSH34E November 2017 – August 2021 OPA2375 , OPA375

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

D|8
- MSOI002K
DSG|8
- MPDS308C
PW|8
- MPDS568
RUG|10
- MPQF216A
DGK|8
- MPDS028E
DDF|8
- MPDS569D

散热焊盘机械数据 (封装 | 引脚)

DSG|8
- QFND141I
RUG|10
- QFND221

订购信息

7.8 Typical Characteristics: OPA2375

at T_A = 25°C, V_S = ±2.75 V, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2, unless otherwise noted.

V_CM = V–

Figure 7-39 Offset Voltage Production Distribution

V_CM = V–

Figure 7-41 Offset Voltage vs Temperature (PMOS Input Pair)

Over full common-mode voltage range

Figure 7-43 Offset Voltage vs Common-Mode Voltage (Full Range)

Figure 7-45 Offset Voltage vs Common-Mode Voltage (Transition Region)

Figure 7-47 I_B and I_OS vs Common-Mode Voltage

Figure 7-49 0.1-Hz to 10-Hz Flicker Noise

Figure 7-51 CMRR and PSRR vs Frequency (Referred to Input)

V_CM = V–

Figure 7-53 PSRR vs Temperature

C_L = 10 pF

Figure 7-55 Closed-Loop Gain vs Frequency

Figure 7-57 Open-Loop Gain vs Output Voltage

Figure 7-59 No Phase Reversal

V_CM = V_S / 2, R_L = 1 kΩ
Gain = +1, 100-mV output step

Figure 7-61 Small-Signal Overshoot vs Load Capacitance

C_L = 20 pF, Gain = 1, V_IN = 100-mVpp, R_L = 1 kΩ

Figure 7-63 Small-Signal Step Response

C_L = 20 pF, Gain = +1, V_IN = 2-V step, R_L = 1 kΩ

Figure 7-65 Large Signal Step Response

C_L = 20 pF, Gain = 1, V_IN = 2-V step

Figure 7-67 Large Signal Settling Time (Positive)

V_CM = 2.5 V
Gain = +1, BW = 80 kHz, V_OUT = 0.5 Vrms

Figure 7-69 THD + N vs Frequency

Figure 7-71 V_OUT vs Sourcing Current

C_L = 10 pF, Gain = +1, V_S= 5.5 V

Figure 7-73 Maximum Output Voltage vs Frequency

Figure 7-75 Quiescent Current vs Supply Voltage

Figure 7-77 Open-Loop Output Impedance vs Frequency

Figure 7-79 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

Figure 7-40 Offset Voltage Drift Distribution

V_CM = V+

Figure 7-42 Offset Voltage vs Temperature (NMOS Input Pair)

Figure 7-44 Offset Voltage vs Common-Mode Voltage (PMOS Input Pair)

Figure 7-46 Offset Voltage vs Power Supply

Figure 7-48 I_B and I_OS vs Temperature

Figure 7-50 Input Voltage Noise Spectral Density vs Frequency

V_S = 5.5 V, V_CM = V– to (V+) – 1.2 V

Figure 7-52 CMRR vs Temperature

C_L = 10 pF

Figure 7-54 Open-Loop Gain and Phase vs Frequency

Figure 7-56 Open-Loop Gain vs Temperature

Figure 7-58 Phase Margin vs Capacitive Load

V_CM = V_S / 2, R_L = 1 kΩ
Gain = –1, 100-mV output step

Figure 7-60 Small-Signal Overshoot vs Load Capacitance

V_IN = 0.6 Vpp, G = –10, V_IN × gain > V_S

Figure 7-62 Overload Recovery

C_L = 20 pF, Gain = –1, V_IN = 100-mVpp, R_L = 1 kΩ

Figure 7-64 Small-Signal Step Response

C_L = 20 pF, Gain = –1, V_IN = 2-V step, R_L = 1 kΩ

Figure 7-66 Large Signal Step Response

C_L = 20 pF, Gain = –1, V_IN = 2-V step

Figure 7-68 Large Signal Settling Time (Negative)

V_CM = 2.5 V
BW = 80 kHz

Figure 7-70 THD + N vs Amplitude

Figure 7-72 V_OUT vs Sinking Current

Figure 7-74 Short-Circuit Current vs Temperature

Figure 7-76 Quiescent Current vs Temperature

A_VDD = 5.5 V, V_ICM = V_OCM = 2.75 V

Figure 7-78 Channel Separation vs Frequency

V_S = 0 to 5.5 V, V_OUT = 0 to 2.75 V

Figure 7-80 Turn-On Time