9.2.1.1 Design Requirements

A SAR ADC, such as the ADS8860 device, uses sampling capacitors on the data converter input. During the signal acquisition phase, these sampling capacitors are connected to the ADC analog input terminals AINP and AINN (pins 3 and 4), through a set of switches. After the acquisition period has elapsed, the internal sampling capacitors are disconnected from the input terminals (pins 3 and 4) and connected to the ADC input through a second set of switches, during this period the ADC is performing the analog-to-digital conversion. Figure 62 shows this architecture.

Figure 62. Simplified SAR ADC Input

The SAR ADC inputs and sampling capacitors must be driven by the OPA2626 to 16-bit levels within the acquisition time of the ADC. For the example illustrated in Figure 61, the OPA2626 is used to drive the ADS8860 at a sample rate of 1 MSPS.