9.2.1.2 Detailed Design Procedure

The circuit illustrated in Figure 61 consists of the SAR ADC driver, a low-pass filter, and the SAR ADC. The SAR ADC driver circuit consists of an OPA2626 configured in an inverting gain of 1. The filter consists of R_FLT and C_FLT, connected between the OPA2626 output and the ADS8860 input. Selecting the proper values for each of these passive components is critical to obtain the best performance from the ADC. Capacitor C_FLT serves as a charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented by the ADC creates a glitch on the filter capacitor, C_FLT. To minimize the magnitude of this glitch, choose a value for C_FLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a minimum settling time. Using Equation 6, a 10-nF capacitor is selected for C_FLT.

Equation 6.

Connecting a 10-nF capacitor directly to the OPA2626 output degrades the OPA2626 phase margin and results in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (R_FLT) to isolate the capacitor, C_FLT, from the OPA2626. R_FLT must be sized based upon several constraints. To determination a suitable value for R_FLT, consider the impact upon the THD resulting from the voltage divider effect from R_FLT reacting with the switch resistance (R_SW) of the ADC input circuit, as well as the impact of the output impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example, Figure 13 can be used to estimate a suitable value for R_ISO. R_ISO represents the total resistance in series with C_FLT, and in this example is equivalent to 2 × R_FLT.