9.2.2.1 Design Requirements

To optimize this circuit for performance, this design does not allow any large signal input transients at the driver circuit inputs for a small quiet-time period (t_QT) towards the end of the previous conversion. The input step voltage can appear anytime from the beginning of conversion (CONVST rising edge) until the elapse of a half cycle time (0.5 × t_CYC). This timing constraint on the input step allows a minimum settling time of (t_QT + t_ACQ) for the ADC input to settle within the required accuracy, in the worst-case scenario. t_QT + t_ACQ is the total time in which the output of the amplifier has to slew and settle within the required accuracy before the next conversion starts. Figure 65 shows this timing sequence.

Figure 65. Timing Diagram for Input Signals