9.2.2.2 Detailed Design Procedure

An ADC input driver circuit consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is used for signal conditioning of the input voltage and the low output impedance provides a buffer between the signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switched-capacitor input stage of the ADC and acts as an antialiasing filter to band-limit the wideband noise contributed by the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the circuit, driven by the following requirements:

• The R_FLT and C_FLT filter bandwidth must be low to band-limit the noise fed into the input of the ADC, thereby increasing the signal-to-noise ratio (SNR) of the system
• The overall system bandwidth must be large enough to accommodate optimal settling of the input signal at the ADC input before the conversion starts

C_FLT is chosen based upon Equation 7. C_FLT is chosen to be 1 nF.

Equation 7.

Connecting a 1-nF capacitor directly to the output of the OPA2626 degrades the OPA2626 phase margin and results in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, R_FLT, is used to isolate the capacitor, C_FLT, from the OPA2626. R_FLT must be sized based upon several constraints. To determination a suitable value for R_FLT, the system designer must consider the impact upon the THD resulting from the voltage divider effect from R_FLT reacting with the switch resistance, R_SW, of the ADC input circuit as well as the impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In this design example, Figure 12 can be used to estimate a suitable value for R_ISO. R_ISO represents the total resistance in series with C_FLT, which in this example is equivalent to 2 × R_FLT.