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ZHCSJY2A June 2019 – September 2019 OPA2834

PRODUCTION DATA.

with P_D = V_CC and T_A ≈ 25°C , gain mentioned in V/V (unless otherwise noted)

Figure 29. Open-Loop Gain and Phase vs Frequency

Measured then fit to ideal 1/f model

Figure 31. Input Noise Density vs Frequency

54000 units at each supply voltage

Figure 33. Input Offset Voltage Distribution

32 units at 5-V and 3-V supply

Figure 35. Input Offset Current vs Ambient Temperature

136 units, –40°C to +125°C

Figure 37. Input Offset Voltage Drift Distribution

See Figure 49,
Recommended value of R_O for targeting 30° phase margin

Figure 39. Output Resistor (R_O) vs C_L

Figure 41. Output Voltage Swing vs Load Resistor

Figure 43. Crosstalk vs Frequency

Figure 30. Closed-Loop Output Impedance vs Frequency

Figure 32. CMRR and PSRR vs Frequency

32 units at 5-V and 3-V supply, Input offset voltage calibrated to 0V at 25°C

Figure 34. Input Offset Voltage vs Ambient Temperature

32 units at 5-V and 3-V supply

Figure 36. Input Bias Current vs Ambient Temperature

32 units at 5-V and 3-V supply

Figure 38. Supply Current vs Ambient Temperature

See Figure 49

Figure 40. Small-Signal Frequency Response vs C_L
With Recommended R_O

32 units at 5-V and 3-V supplies

Figure 42. Input Offset Voltage vs Input Common-Mode Voltage

Figure 44. Input Offset Mismatch (Between Channel A and Channel B) Distribution